EVAL-AD5761RSDZ

Hi,

I am currently working with the EVAL-AD5761RSDZ. I am trying to control the DAC with a Python script running on a Raspberry Pi.

As far as I know I have to write to the control register after powering up. By sending 0x04 04 11 the DAC should be configured to the output range from 0V to 10V.  Then I can use the write and update command, 0x03 ff ff, to set the voltage output to its maximum. However, the output remains unchanged at 0V. I have also tried to start with a "software full reset" command, but the result is the same. While checking the connections of the DAC I couldn't find any issues. The signal on the MOSI line goes into the chip, as well as the CLK signal, the sync signal and the provided power.

Do you have any idea what I could be doing wrong or how I can solve this problem?


Parents
  • 0
    •  Analog Employees 
    •  Super User 
    on Nov 3, 2020 3:12 AM

    Hi, 

    Have you checked the jumper settings on the EVAL-AD761RSDZ? What's your setting for LK1 to LK4?

    How about the supply connectors J1, J2, J5? What's your voltage setting on these pins?

    Can you also show an OSC capture of your SPI transactions? 

    Are you using internal reference, external on-board reference, or external reference?

    Hope you can answer the above queries so I can helpo you out.

    Best regards,

    Ian

  • Hi,

    Yes I did checked the jumper settings, but I feel like that this is not the cause of my Problem. The Links of LK2 and LK14 are removed. On the other hand, the Links of LK7 and LK8 are inserted and the Links of LK_AVDD, LK_AVSS, LKDVCC, LK_REF, LK_VOUT+, LK_VOUT- are conected to B.

    Power is supplied via the  PVIN_3V-15V connector. The input voltage and messured voltage on these conectors is 10V.  The voltage messured on the Vss Pin is -11V and on the VDD Pin 21V. The Voltage at the DVcc Pin lays around 2.3V.

    I am using an internal reference selected by position B of the LK_REF Pins.

    This is the Date send to initilize the DAC.

    And this is the write and update command.

    The yellow signal is the clock signal and the green signal is the MOSI signal.

    I hope that this answers your questions. If not, please let me know what else you need.

    Best regards,

    Nils

  • 0
    •  Analog Employees 
    •  Super User 
    on Nov 6, 2020 3:58 AM in reply to Nils

    Hi Nils, 

    I don't have an eval board with me right now. I'm curious as to why the DVcc is around 2.3V. I looked through the schematic and found that with your current jumper settings, there is no actual supply going into the DVCC pin. I'm thinking the LK_DVCC pin should be on pos A, that will give a good 5V into the DVCC pin.

    I also noticed that the MOSI is set at the falling clock edges. This will pose a problem as the AD5761R also reads the data on the falling clock edge. In this case, we need to make sure that the data is already valid on the falling edge so it would be better for the MOSI to set date on the rising edge. You can refer to the Serial Interface section of the datasheet. 

    Let me know if the above works. 

    Best regards,

    Ian

  • Hello Ian,

    I changed the position of the LK_DVCC pin with the result that 5V were measured at the DVCC pin.

    Regarding the operating modes for the MOSI line I have two options. Option one is selected in the last snapshots and the second mode is selected in this picture.

    Unfortunately these adjustments did not solve my problem. I still have a VOUT of 0V. Do you have any other suggestions what I can try?

    Thank you very much for your efforts, I really appreciate it.

    Best regards,

    Nils

  • 0
    •  Analog Employees 
    •  Super User 
    on Nov 10, 2020 4:00 AM in reply to Nils

    Hi Nils, 

    Hardware setup and SPI mode should be ok now. 

    I'm reviewing your SPI commands, 

    0x04 04 11 - You should enable the internal reference (IRO) bit, it should be 0x04 04 31.

    The power-up voltage (PV) is set to 10: full scale at startup. so you might not need the 2nd spi transaction. 

    Let me know if this works.

    Best regards,

    Ian

  • Hi Ian,

    I did what you said, but I still get 0V as output. Are you sure about the SPI command? The datasheet says that DB5 should be 0 for all control register commands.

    I also checked my hardware setup and changed the LK_REF pin to position B to enable on-board reference. But there is still no change in the output value.

    Do you have any other suggestions what might help?

    Best regards,

    Nils

  • 0
    •  Analog Employees 
    •  Super User 
    on Nov 16, 2020 1:53 AM in reply to Nils

    Hi Nils, 

    You are using EVAL-AD5761RSDZ board correct? The DAC in the board should be AD5761R (with internal reference) DB5 of control register is the IRO (internal reference output). which should be set to 1 together with LK_REF at position B. 

    I'd like you to try to start with a software reset on spi followed by 0x04 04 31. After this command, you should be getting 2.5V out of the reference pin TP10. 

    You could refer to this FAQs: DAC Communication Troubleshooting. Next to check would be to do a readback of the control register to assure you have proper SPI comm.

    Best regards,

    Ian

Reply
  • 0
    •  Analog Employees 
    •  Super User 
    on Nov 16, 2020 1:53 AM in reply to Nils

    Hi Nils, 

    You are using EVAL-AD5761RSDZ board correct? The DAC in the board should be AD5761R (with internal reference) DB5 of control register is the IRO (internal reference output). which should be set to 1 together with LK_REF at position B. 

    I'd like you to try to start with a software reset on spi followed by 0x04 04 31. After this command, you should be getting 2.5V out of the reference pin TP10. 

    You could refer to this FAQs: DAC Communication Troubleshooting. Next to check would be to do a readback of the control register to assure you have proper SPI comm.

    Best regards,

    Ian

Children
  • Hi Ian,

    I have to correct myself. I chose position A for the LK_REF pin ("Position A selects the source from the on-board ADR4525 reference.")

    Nevertheless I tested your command in both configurations. At position A I could measure the expected 2.5V, but I had no higher output voltage than 0V.

    I am a litlle bit confused by the results I get after using the readback command (0x0C XX XX). The MISO line is high for the all 24 Bits.

    Here is a snaphot of the CLK(green), MOSI(red), MISO(yellow)

    The first three bytes are the readback command and the last three bytes are the bytes red by the Raspberry (0xFF FF FF).

    I also looked at a standerd write command and the MISO line was high during the write cycle.

    Is this normal that the SDO Pin is set high for all SPI commands? Or does this mean that I have a fundamental Problem with the SPI communication?

    Best regards,

    Nils

  • 0
    •  Analog Employees 
    •  Super User 
    on Nov 17, 2020 12:01 AM in reply to Nils

    Hi Nils, 

    Let me clear up first, 0x04 04 31 command enables the internal reference. So your LK_REF should be at pos B. You should also check the VREF output in this case if there is a 2.5V present. 

    If you'll use LK_REF at pos A, then the control reg write should be 0x04 04 11. 

    This SDO/MISO is not normal. It seems the SDO goes high right before you start your SPI comm. you might want to check your SPI function on the master.

    Have you tried using a different master board? 

    Or use the same master board to control a different SPI device. I hope to isolate whether the master or the AD5761 digital circuitry is the problem. 

    By the way, I don't see the /SYNC signal on your SPI waveforms. Can you check if it meets the minimum timings as shown in Figure 2 of the datasheet?

    Best regards,

    Ian

  • Hi Ian,

    Thank you very much for the clarification with the VREF setup.

    I did not add the SYNC line OSC, so it is not visible in the snapshots. Before I contacted you, I checked the times listed in the data sheet and found no abnormalities.

    I feel like the master is not necessarily the reason for the behavior of the SDO line. I tested the output of the line once with the master connected to the SDO pin and once wtih the Raspberry not connected. In both cases the MISO line was set to high during SPI communication.

    In addition to that, I tested the SPI communication with an ADC and it worked without any problems.

    No, I have not tried a different master board yet. But I thought on testing the DAC with the SDP board and the included software once the SDP board arrives.

    I have a question regarding the diodes built in: What do the diodes indicate and when are they supposed to be on?

    Best regards,

    Nils

  • 0
    •  Analog Employees 
    •  Super User 
    on Nov 19, 2020 12:09 AM in reply to Nils

    Hi Nils, 

    I have a question regarding the diodes built in: What do the diodes indicate and when are they supposed to be on?

    The diodes on the IO pins act as protection, in case a voltage higher than the +supply rail or a voltage lower than the -supply rail (or in our case, GND)  is applied to them, the diodes would turn on. 

    You could do a diode check using a DMM, (applying the +terminal to DVCC and the -terminal to the IO pins) to see if the protection diodes are still OK. You should get a ~0.7V reading. But looking back at your scope shots, I see that SDO only comes high when you start the spi transaction. 

    What are the states of the other IO pins? (/LDAC, /CLEAR, /RESET) They should be biased properly from the master and not left hanging. 

    Best regards,

    Ian

  • Hi Ian,

    The diodes on the IO pins act as protection, in case a voltage higher than the +supply rail or a voltage lower than the -supply rail (or in our case, GND)  is applied to them, the diodes would turn on.

    In that case I think this could be the problem. The diodes are an while I am supplying 10V via the PVIN connector . While operating with the current pin setup I messure around -11V at the LED_AVSS Pin and 21V at the LED_AVDD Pin. They are also on when the evalution board is connected to the SDP board.

    What are the states of the other IO pins? (/LDAC, /CLEAR, /RESET) They should be biased properly from the master and not left hanging. 

    These Pins are set to high via the Python script and the voltage messured lays around 2.8V. This is how it should be, isn't it?

    Best regards,

    Nils