According to the AD5592R datasheet the Conversion time (tconv) is maximum 2us and the Track Time (ttrack) is minimum 500ns.
If I understand this correct, this tells me the ADC needs maximum 2 us for a conversion. This is not a requirement for how fast the next toogle should come on the SYNC pin in FIGURE 44? If it had been so then I would have needed 16 clocks in 2us minus a track time of 500ns and this would have set the SCLK frequency of minimum 11 MHz… Correct? So can you verify the following statement: If I comply on the req. in Table 4 and use a Track Time of minimum 500ns I can then use a SCLK frequency of 1MHz since this will be more than the maximum 2us conversion time requirement.
The figure in post 26528 is also a bit confusing wrt the 2us req.
2us conversion time minimum is from first SYNC falling edge to the next SYNC falling edge.
500ns track time is before the start of the conversion, which means before the SYNC falling edge..