Looking at the timing diagram, it seems that when /CS is low, the latch is transparent so everything on the data bus will reflect on output. /CS going high will just latch the latest value and determine…
Mochi said:Is it safe to assume that the data is actually latched at the rising edge?Is there any inconvenience if the L level state of the /CS terminal continues for a long time (500mS, etc.)?
Yes, this is correct,. Data is latched on the rising edge. There is also no problem if /CS L level is longer than the minimum specified. But it should be well noted that whilst your /CS is L, data may change on the data bus and we need to make sure that the data is valid (not changing) for a minimum amount of time, t(ds), before /CS transitions from L → H, plus a minimum hold time, t(dh), after /CS L → H. THis is to make sure valid data is latched onto the device's registers.
Looking at the timing diagram, it seems that when /CS is low, the latch is transparent so everything on the data bus will reflect on output. /CS going high will just latch the latest value and determine the final output level.
To avoid unwanted output changes, it would be best to only set CS low during the time you want to set the data and return it high once again.
Sorry about the confusion from my previous response.