AD767 STB INPUT

Hi

I have a question about the AD767.
I know this device is not a new device.
This device is "not recommended for new designs".
I would appreciate it if you could answer my customer's question.

The datasheet is instructed to strobe the input data with a pulse of H → L → H.
Is it safe to assume that the data is actually latched at the rising edge?
Is there any inconvenience if the L level state of the /CS terminal continues for a long time (500mS, etc.)?

Thanking you in advance
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    •  Analog Employees 
    on Oct 6, 2020 2:16 AM 1 month ago

    Hi, 

    Is it safe to assume that the data is actually latched at the rising edge?
    Is there any inconvenience if the L level state of the /CS terminal continues for a long time (500mS, etc.)?

    Yes, this is correct,. Data is latched on the rising edge. There is also no problem if /CS L level is longer than the minimum specified. But it should be well noted that whilst your /CS is L, data may change on the data bus and we need to make sure that the data is valid (not changing) for a minimum amount of time, t(ds), before /CS transitions from L → H, plus a minimum hold time, t(dh), after /CS  H. THis is to make sure valid data is latched onto the device's registers. 

    Best regards,

    Ian

  • Thank you
    Excuse me, but please tell me only one.
    When / CS = L, the data bus is not transparent to the output, isn't it?

    Best regards
  • +1
    •  Analog Employees 
    on Oct 7, 2020 1:01 AM 1 month ago in reply to Mochi

    Hi,

    Looking at the timing diagram, it seems that when /CS is low, the latch is transparent so everything on the data bus will reflect on output. /CS going high will just latch the latest value and determine the final output level. 

    To avoid unwanted output changes, it would be best to only set CS low during the time you want to set the data and return it high once again.

    Sorry about the confusion from my previous response.

    Best regards,

    Ian

Reply
  • +1
    •  Analog Employees 
    on Oct 7, 2020 1:01 AM 1 month ago in reply to Mochi

    Hi,

    Looking at the timing diagram, it seems that when /CS is low, the latch is transparent so everything on the data bus will reflect on output. /CS going high will just latch the latest value and determine the final output level. 

    To avoid unwanted output changes, it would be best to only set CS low during the time you want to set the data and return it high once again.

    Sorry about the confusion from my previous response.

    Best regards,

    Ian

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