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AD5644R - SPI power-up time delay

Jenda
on Sep 24, 2020

Hi,

I haven't found in the datasheet any info about this DAC's SPI power-up time delay.. There is only "Power-Up Time: 4 us", but its not specified there, whether it is applicable also to the SPI control.

The thing is when I used 200 us start delay, the SPI writes hadn't any impact. My SPI init command are: set internal reference on, set DAC channels to some non zero values.

When I use 400 us start delay it works just fine.

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  • 0
    •  Analog Employees 
    •  Super User 
    on Sep 25, 2020 6:11 AM

    Hi, 

    The power-up time spec is only applicable to the DAC output when it comes from a power-down mode. 

    How do you set your start delay? is it from the time you command your VDD supply to turn ON or from the time that VDD is already at the specified value? 

    I suggest including a software reset in your init command. It should be the first command in the sequence. 

    Best regards,

    Ian

  • 0 on Sep 25, 2020 10:17 AM in reply to iandal

    Hi Ian,

    so there is no real power-up time specified for the SPI interface?

    Actually it is a delay from FPGA boot, so it will be even longer than that (something like VDD_delay + FPGA_boot_delay + MY_DELAY).

    By software reset you mean sending a reset command to the DAC via SPI? And what difference will it make if the SPI still wont be ready?

    Thanks for your suggestions.

  • 0
    •  Analog Employees 
    •  Super User 
    on Sep 25, 2020 10:43 AM in reply to Jenda

    Hi, 

    Jenda said:
    so there is no real power-up time specified for the SPI interface?

    Can't seem to find it in the datasheet too. I'll try to check if I can find this spec. Is this timing crucial in your application? 

    Jenda said:
    By software reset you mean sending a reset command to the DAC via SPI? And what difference will it make if the SPI still wont be ready?

    Well, it can make sure that the registers are reset to default in case something happens during power ON. Unless it impacts the application, it doesn't hurt to be more careful. Let me know if it works. Slight smile

    Best regards
    Ian

  • 0 on Sep 25, 2020 10:55 AM in reply to iandal

    The timing isnt exactly crucial in our application, I just dont like some random "long enough" delay, that might not work in all cases.. I wont have any possibility to check that the DAC init has been succesfull as the SPI there has only one direction (MOSI).

  • +1
    •  Analog Employees 
    •  Super User 
    on Sep 29, 2020 7:36 AM in reply to Jenda

    Sorry about that. We do not characterize this time as it is typically not needed… in other words, the MCU or FPGA initialization should take a similar or longer time. That being said, the initialization depends as well on supplies ramp rates… if the supply is slow, it will take a longer time to initialize.

    You could check the ramp time of your VDD upon enabling it until it reaches the minimum VDD spec 4.5V or 2.7V (if you are using the "-3" version). It would be best if this delay is accounted for on your VDD_delay. 400us seems reasonable but since there is no feedback on your SPI line, increasing the delay is safer. 

  • 0 on Sep 29, 2020 2:09 PM in reply to iandal

    ok, thanks for the answer Ian.

    Best regards

    Jenda

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