AD5292 High Impedance Mode - How To Get Back To Normal?

Hi,

If I set the AD5292 into the high impedance mode (0x8001, followed by 0x0000), how do I get it back to normal mode?

Best Regards,
Gerd

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  • 0
    •  Analog Employees 
    on Sep 28, 2020 8:43 AM

    Hi ,

    Someone is currently looking into this and will respond as soon as possible.

    Cheers

    Ivan

  • 0
    •  Analog Employees 
    on Oct 9, 2020 6:25 AM in reply to isantos

    When you provide any new command following 0x8001 and 0x0000, it will come back to normal mode.

  • Ok, then I would need a command that does nothing but wakes the SDO pin up.

    Like command 8 from table 11 with D0 set to 0?

    I assume a terminated command (_SYNC going high after non-multiple-of-16 clock cycles) doesn't wake SDO up either?

    And what happens if an AD5292 receives an all 1 command? Because if the IC before it in the chain has a disabled SDO, the DIN will be high for all 16 clock cycles.

  • While I am still interested in the answers to above questions...

    In high-impedance-mode, the SDO behaves no different than if the IC was active in a normal mode, but the logic signal active on the SDO pin was just high (1), right?

    What if I set DIN to 1 and put 257 clock cycles on CLK and then raise _SYNC?

    As 257 is no multiple of 16, the ICs would discard the command and because of more than 256 ones having been clocked into the daisy chain, the SDOs of all ICs will be at logic 1, effectively drawing quasi zero current. Correct?

  • 0
    •  Analog Employees 
    on Oct 13, 2020 5:41 AM in reply to GerdF

    Like command 8 from table 11 with D0 set to 0?

    >> Yes.

    I assume a terminated command (_SYNC going high after non-multiple-of-16 clock cycles) doesn't wake SDO up either?

    And what happens if an AD5292 receives an all 1 command? Because if the IC before it in the chain has a disabled SDO, the DIN will be high for all 16 clock cycles.

    >> If an all '1' command is received, the device will simply ignore it as it is not a valid command, unless it is daisy chain mode. Do note that the each device in the daisy chain will give out proper data on SDO based on the command in the previous frame for the first 16 clocks..

  • 0
    •  Analog Employees 
    on Oct 13, 2020 5:42 AM in reply to GerdF

    A valid command will be properly executed by the device and the others will be simply ignored. 

    As 257 is no multiple of 16, the ICs would discard the command and because of more than 256 ones having been clocked into the daisy chain, the SDOs of all ICs will be at logic 1, effectively drawing quasi zero current. 

    >> You will need data equivalent to 17 devices to make it work. Please see my previous response. 

  • Like command 8 from table 11 with D0 set to 0?

    >> Yes.

    So after sending command 8 sixteen times, the chain will be ready again.

    >> If an all '1' command is received, the device will simply ignore it as it is not a valid command

    And during this wake-up action, the ICs that are in the chain behind an IC that is still in high impedance mode will receive all-1 commands and ignore them.

    unless it is daisy chain mode.

    Aaah, wait, I am explicitly talking about a daisy chain.

    What happens there differently? If the IC ignores the all-1 command, it should "output" all-1s, because it's still in high impedance and the pull-up resistor makes it ones at DOUT.

    Once its DOUT is awoken by the command 8, it should then give out just this command 8 during the next 16 clock cycles, waking up the DOUT of the next IC. Or do I misunderstand that?

    As 257 is no multiple of 16, the ICs would discard the command and because of more than 256 ones having been clocked into the daisy chain, the SDOs of all ICs will be at logic 1, effectively drawing quasi zero current. 

    >> You will need data equivalent to 17 devices to make it work. Please see my previous response.

    The 257 all-1s (16*16+1) were not meant for ending the high impedance mode.

    If I keep the ICs in normal mode, any DOUT at logic 0 would draw current. But if I clock in 257 bits, each having logic 1, all the shift registers would be filled with 1s. Then there could be no current draw by the DOUT pins.

    If I knew for sure that all-1 commands are really ignored, I could use 17 times 16 all-1 bits and finish the communication orderly.

    But who knows if some designer hasn't used all-1 commands for internal purposes (testing, etc.).

    So if I terminate the transfer by pulling _SYNC high after a non-multiple-of-16 clock cycles, I can be really sure that there is no command executed, but the shift registers (including the DOUT pin determining flip flops) would definitely be high, so no current drawn by the DOUT pins.

    And as the ICs are not in high impedance mode, I would not have to bring them back to normal mode, because they are already there and ready for the next command.

Reply
  • Like command 8 from table 11 with D0 set to 0?

    >> Yes.

    So after sending command 8 sixteen times, the chain will be ready again.

    >> If an all '1' command is received, the device will simply ignore it as it is not a valid command

    And during this wake-up action, the ICs that are in the chain behind an IC that is still in high impedance mode will receive all-1 commands and ignore them.

    unless it is daisy chain mode.

    Aaah, wait, I am explicitly talking about a daisy chain.

    What happens there differently? If the IC ignores the all-1 command, it should "output" all-1s, because it's still in high impedance and the pull-up resistor makes it ones at DOUT.

    Once its DOUT is awoken by the command 8, it should then give out just this command 8 during the next 16 clock cycles, waking up the DOUT of the next IC. Or do I misunderstand that?

    As 257 is no multiple of 16, the ICs would discard the command and because of more than 256 ones having been clocked into the daisy chain, the SDOs of all ICs will be at logic 1, effectively drawing quasi zero current. 

    >> You will need data equivalent to 17 devices to make it work. Please see my previous response.

    The 257 all-1s (16*16+1) were not meant for ending the high impedance mode.

    If I keep the ICs in normal mode, any DOUT at logic 0 would draw current. But if I clock in 257 bits, each having logic 1, all the shift registers would be filled with 1s. Then there could be no current draw by the DOUT pins.

    If I knew for sure that all-1 commands are really ignored, I could use 17 times 16 all-1 bits and finish the communication orderly.

    But who knows if some designer hasn't used all-1 commands for internal purposes (testing, etc.).

    So if I terminate the transfer by pulling _SYNC high after a non-multiple-of-16 clock cycles, I can be really sure that there is no command executed, but the shift registers (including the DOUT pin determining flip flops) would definitely be high, so no current drawn by the DOUT pins.

    And as the ICs are not in high impedance mode, I would not have to bring them back to normal mode, because they are already there and ready for the next command.

Children
  • 0
    •  Analog Employees 
    on Oct 15, 2020 5:19 AM in reply to GerdF

    You can purchase the Eval board to verify all the requirements that you are looking for.

    In the daisy chain mode, every device in the daisy chain begins outputting data on SDO for 1st 16 clks based on the previous command. so if the total number of clocks are 16 times the device count, then the last device SDI input will be the SDO data of the first device. So, if you want the system to ignore that, you need to feed 16 additional clocks to pop this data out.

    Device will ignore all invalid commands. You can verify the same with the Eval board. Had it not been the case, it would have been difficult to implement the daisy chain mode for such devices, at it would lead to weird behaviour in any system.

    Yes, if you can make the last bit on each device SDO to be '1', then the current drawn by the SDO will be negligible.