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AD5292 Power-Up - Do The Terminals Start Open Circuit And When Do They Get Connected?

Hi,

When the AD5292 has no supply voltage applied, I assume that all analog switches are off and so the A, B and W terminals are disconnected.

While the datasheet says that "after VLOGIC is powered, the power-on preset activates, restoring the 20-TP memory value to the RDAC register.", wouldn't that require reading the 20-TP memory, which requires the high voltage on the VEXT_CAP pin, which is drawn from VDD.
So if VDD is still down, would that mean that VDD must be up in order for the terminals are connected to the internal resistor strings?
Would the power-up cycle then only start when VDD reaches a certain voltage?

And how about when the switches are being actually connected? Would that happen at some VDD-VSS threshold value? or would they be connected directly after the power-up and then only become lower-ohmic with the further rising supply voltage?

Regards,
Gerd
 

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  • Yes, VDD need to be powered up for the 20-TP memory to be restored to RDAC register. Once the VDD-VSS has crossed 90% of its FS value, the switches on the A-W-B termiinals will be connected. 

    Internal Power-up reset is dependent on Vlogic or RESET being high and not on VDD. So, if the VDD is not powered up while the Vlogic and RESET are up, the power on reset will still happen and, the read back from 20-TP memory to RDAC register will be in undefined state and you need to provide a RESET toggle to reload the RDAC register.

  • Then why don't you provide this information in the datasheet?

    "The ideal power-up sequence is GND, VSS, VLOGIC and VDD, the
    digital inputs, and then VA, VB, and VW. The order of powering up VA, VB, VW, and the digital inputs is not important as long as
    they are powered after VDD, VSS, and VLOGIC.
    Regardless of the power-up sequence and the ramp rates of the
    power supplies, after VLOGIC is powered, the power-on preset activates, restoring the 20-TP memory value to the RDAC register."

    The first sentence should read "The ideal power-up sequence is GND, VSS, VDD, VLOGIC, the digital inputs, and then VA, VB, and VW."

    And the last sentence should read "Regardless of the power-up sequence and the ramp rates of the other power supplies, after VDD is brought above XX volts and subsequently VLOGIC is powered, the power-on preset activates, restoring the 20-TP memory value to the RDAC register."

    This would have saved me from now having to redesign the circuit after the PCB is like 3 days before Gerber tape-out.

  • RESET is a part of digital inputs as mentioned in the power-on sequence and so the power-on reset will not happen until the RESET is brought high. Now, if the ideal sequence is not followed and digital inputs come up before Vlogic, then Vlogic power up will trigger the power on reset.

  • But VLOGIC will not correctly power up if VDD is not yet there.

    And if RESET is connected to VLOGIC, RESET is also of no help. So either I have to change the power up sequence (having to check with all other ICs if that would be ok) or I have to drive RESET separately (without having left the space for another track) or put an RC low-pass between VLOGIC and RESET (again not having the space)...

  • Vlogic will power up even if the VDD is not connected. It is the TP memory block that will not be loaded if the VDD is not yet there.

    Now if the RESET is tied to VLOGIC and VDD comes up later, then you can do a software RESET using command 4 as mentioned in the table 11.

  • Ok, I think that might be a solution. Thanks for reminding me of it.

    Am I correct in assuming that during the actual (hardware) reset (while /RESET is low or while VLOGIC is not yet above the power on reset threshold) all the analog switches are in the open state and the A, B and W terminals are actually disconnected?

    I use one of the DigiPOTs as RSET of an LT3045. So I would either have the SET pin shorted to GND until the DigiPOT is up and running or I would have to disengage the enable pin of the LT3045 in order not to fry everything behind the regulator. And this short to GND would have to be something I can actively release but that would in any case be a short from applying power to the circuit until I release it.

    If VLOGIC goes up before VDD is above 9V (like if VDD is rising slowly because of heavy noise filtering and VLOGIC is just branched from VDD with an according regulator, so both reach 2.7V at about the same time and VDD is thereafter just going on to relatively slowly rise to 15V), what would be the likely state of the potentiometer once the power on reset is activated?

    As VDD will be way below 5 volts, it cannot supply the 5.5V for the VEXT_CAP voltage and drive no current through the diodes. So I assume the diodes would be read as all open circuit.
    Would this result in an all zero wiper setting or rather an all ones?

  • Am I correct in assuming that during the actual (hardware) reset (while /RESET is low or while VLOGIC is not yet above the power on reset threshold) all the analog switches are in the open state and the A, B and W terminals are actually disconnected?

    Yes, this is correct.

    If VLOGIC goes up before VDD is above 9V (like if VDD is rising slowly because of heavy noise filtering and VLOGIC is just branched from VDD with an according regulator, so both reach 2.7V at about the same time and VDD is thereafter just going on to relatively slowly rise to 15V), what would be the likely state of the potentiometer once the power on reset is activated?

    The wiper position will be in undefined state as the RDAC register input will not be correctly loaded at VDD < 8V. 

    As VDD will be way below 5 volts, it cannot supply the 5.5V for the VEXT_CAP voltage and drive no current through the diodes. So I assume the diodes would be read as all open circuit.

    Which diodes are you referring to? 

  • Which diodes are you referring to? 

    Might be diodes or fuses. The nonvolatile memory elements.

    I assume that it is a one-time-programmable technology, otherwise it would not be limited to 20 times programming (there would be 20 times the required number of bits and with each new nonvolatile programming step the last programmed row of bits is marked as discarded.
    If it was an EEPROM technology, many more permanent programming cycles would be possible.

    So with the (relatively) high voltage and programming current there are either fuses burnt open or zenerdiodes  heated until they are alloyed into kind of tunnel diodes resembling something like a short circuit (I think there are one or two further possibilities, but that's pretty much it). Sometimes fuses and zeners are combined, but that is quite rare.

    Now if the (a little less) high voltage required for reading the status of the OTP elements is not present, I assume that the readout electronic cannot establish the voltage for reading a one (or a zero, depending on the implementation) and all bits would likely be the same value (at least if VDD is extremely below 9V as it would be with 2.7V, while voltages approaching the minimum required value would then lead to undefined states until above some voltage the correct values would be read).

  • Yes, the TP elements will be in undefined state with VDD <9V.

  • I have a follow-up question regarding this issue:

    If the supply voltages are taken down (VSS, VDD, VLOGIC), at some point the analog switches will become open and the terminals A, B and W will be open circuit.

    Unfortunately, the datasheet does not give a value for that, like a brownout voltage specification.

    The AD5292 needs 9V VDD (above VSS) and 2.7V VLOGIC for normal operation.

    How much lower might these voltages get during operation without the terminals becoming open circuit (switches no longer working due to the voltage falling below the threshold voltage) or the resistances taking on weird values (RDAC register no longer able to hold its values)?

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  • I have a follow-up question regarding this issue:

    If the supply voltages are taken down (VSS, VDD, VLOGIC), at some point the analog switches will become open and the terminals A, B and W will be open circuit.

    Unfortunately, the datasheet does not give a value for that, like a brownout voltage specification.

    The AD5292 needs 9V VDD (above VSS) and 2.7V VLOGIC for normal operation.

    How much lower might these voltages get during operation without the terminals becoming open circuit (switches no longer working due to the voltage falling below the threshold voltage) or the resistances taking on weird values (RDAC register no longer able to hold its values)?

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