AD5680 update anomalies

Hi-

I moved this question to the Precision DACs community.  Please continue the discussion here.

Regards,

AndyR

EngineerZone Community Manager

Hi,

What load conditions are you operating under? The Maximum settling time for the device is 85 microseconds assuming the line capacitance is less than 200pF and the resistance is more than 2kOhms. Could you provide a schematic we can take a look at?

If you are looking at a part with similar performance look at the AD5541A or the AD5542A. You will need to also choose an output amplifier. I would recommend the AD5686 low noise op amp for the output. A reference buffer would also be needed but this level of settlng, twinned with the accuracy, should be achievable.

Regards,

Padraic

Padraic

I've uploaded the schematic and three scope shots:

1) The result (pin 6 of U600 op-amp) of sending a single 24-bit serial word, changing from 0xE7960 to 0x186a0 (18-bit DAC values, -100000 to +100000 decimal).

   Trace 1 = analog value; Trace 2 = DIN; Trace 3 = SYNC~.

2) The result of sending continuous 24-bit values (all identical), every 2 microseconds.  Same signals as 1).

3) Expansion of a single 24-bit transmission in 2).  Trace 1 is SCLK.

The overshoot on the traces is due to the scope ground leads, not a PCB problem.

Thanks for your help.

Carl

Hi Carl,

I wasnt able to see your response. Can you resend the info please?

I cannont comment on 1) as I have not recieved any attachment.

2) The result of sending continuous 24-bit values (all identical), every 2 microseconds:

The settling time is the time taken for the output to reach its final value after the write sequence completes. The specification is 85 micro secs max. If we write to a part while it is in the process of responding/settling to a previous write, the output will sart to respond to latest write regardless of whether the output has settled to the previous target. If you want the part to settle at the output you need to wait approx 83.3 micro secs. You can write quickly to the digital interface but the output or analog section will not respond quick enough.

Thanks,

Padraic

Padraic

I was able to upload the files on a second try (see the previous post).

Comments?

Thanks,

Carl

I am seeing the exact same behaviour for the AD5680 parts in my product's system, as Carl observed in his.
If a value is written to the DAC at intervals of more than 250uS then it works fine and the analog output is stable.
If the DAC is updated more frequently than this, then the analog output voltage switches between multiple states in a cyclical pattern.
This does not seem to be related to the 85us settling time for analog step-changes, as even repeatedly sending the same digital value to the DAC causes this problem.
I would appreciate it if Analog Devices could comment on this in a timely manner.

Hi,

Do you have any plot showing the behavior?

Additionally, the DS mention that the DAC update for the interpolation is around 10kHz... which makes me feel that the limitation you mentioned (fupdate < 4kHz) is related to the internal digital engine.

Best Regards,

Miguel

This (slightly angled) photo of my oscilloscope's screen shows what happens if I write the same value (0x20000) to the DAC repeatedly at 1Mbps, and a gap between writes of 150us.
The bright line across the top is the correct output voltage of half-rail corresponding to 0x20000. (D17..D0).
We can also see that the DAC erroneously produces various other output voltage levels.

If the gap between writes is increased to 500us, the anomalies all go away.

I have tried capturing the SPI interface signals with a logic analyser and they all look fine and consistent.
I am not commanding a step-change in voltage output, so the 85us settling time shown in the datasheet should be irrelevant.
The two LSBs of the commanded setting are both zero, so the output interpolation should be OFF.

This looks like a silicon bug to me. Writing a new value to the SPI before the last one has been processed seems to upset the internal state-machine of the AD5680, even if the written value is the same as the previous value. If so, this is a pretty poor chip design. There seems to be no mention of this bug/feature on the datasheet, and I can't find an errata sheet for this chip.

PS: Here is a photo of the Logic analyser screen showing the DIN, SCLK, and SYNC lines.

Everything in the digital domain looks sensible to me.

Hi,

The captures seems to correlate the behavior described.

I personally believe the devices was not designed to operate in this way (multiples updates), and probably there is an internal race condition that triggers this situation.

I'll request an EVB and see what can I find.

Regards,

Miguel