ADAU1966 - important questions


I am going to connect ADAU1966 DAC and ADAU1442/1445 Sigma DSP together and I have some questions.

1) On page 15 of ADAU1966 documentation we can read:

"If the ADAU1966 is to be used in direct MCLK mode, the PLL can be powered down in the PDN_THRMSENS_CTRL_1 regiter. For direct MCLK mode, a 512 × FS (referenced to 48 kHz mode) master clock must be used as MCLK, and the CLK_SEL bit in the PLL_CLK_CTRL1 register must be set to b1."

But is it still needed circuit from Figure 8 (between LF and PLLVDD pin) ? Maybe LF and PLLVDD pin may be left unconnected or tied to ground ?

2) In the documentation is missing figure of the oscillator circuit similar to that can be found in the ADAU1442/1445 datasheets (Figure 9, page 21). I don't know for example if 100 ohm resistor serial with XTALO is necessary or not. I don't have information about load and stray capacitance, too.

3) I'm not sure if pins AVDD1 to AVDD4 are connected together inside the ADAU1966 or not ?

4) Which solution is better to get best audio performance (SRC inside ADAU1442/1445 will be enabled) ?

a) ADAU1966 MASTER, ADAU1442/1445 SLAVE

ADAU1966 LRCLK - OUT, ADAU1442/1445 LRCLK - IN

ADAU1966 MCLKO -> ADAU1442/1445 XTALI

b) ADAU1966 SLAVE, ADAU1442/1445 MASTER

ADAU1966 LRCLK - IN, ADAU1442/1445 LRCLK - OUT

ADAU1442/1445 CLKOUT -> ADAU1966 MCLKI


Piotr Szymkowiak