ADAU1966 - important questions

Hi,

I am going to connect ADAU1966 DAC and ADAU1442/1445 Sigma DSP together and I have some questions.

1) On page 15 of ADAU1966 documentation we can read:

"If the ADAU1966 is to be used in direct MCLK mode, the PLL can be powered down in the PDN_THRMSENS_CTRL_1 regiter. For direct MCLK mode, a 512 × FS (referenced to 48 kHz mode) master clock must be used as MCLK, and the CLK_SEL bit in the PLL_CLK_CTRL1 register must be set to b1."

But is it still needed circuit from Figure 8 (between LF and PLLVDD pin) ? Maybe LF and PLLVDD pin may be left unconnected or tied to ground ?

2) In the documentation is missing figure of the oscillator circuit similar to that can be found in the ADAU1442/1445 datasheets (Figure 9, page 21). I don't know for example if 100 ohm resistor serial with XTALO is necessary or not. I don't have information about load and stray capacitance, too.

3) I'm not sure if pins AVDD1 to AVDD4 are connected together inside the ADAU1966 or not ?

4) Which solution is better to get best audio performance (SRC inside ADAU1442/1445 will be enabled) ?

a) ADAU1966 MASTER, ADAU1442/1445 SLAVE

ADAU1966 LRCLK - OUT, ADAU1442/1445 LRCLK - IN

ADAU1966 MCLKO -> ADAU1442/1445 XTALI

b) ADAU1966 SLAVE, ADAU1442/1445 MASTER

ADAU1966 LRCLK - IN, ADAU1442/1445 LRCLK - OUT

ADAU1442/1445 CLKOUT -> ADAU1966 MCLKI

Regards,

Piotr Szymkowiak

Parents
  • Hi, Coleman

    Thank you with comprehensive answers to points from 1) to 3).

    But I still have doubts about the point 4). I have just read carefully the documentation of ADAU1442/1445 and there is written (page 21):

    "The on-board oscillator is designed to work with a 256×FS NORMAL master clock, which is 12.288 MHz when FS NORMAL is 48 kHz"

    "CLKOUT can output 256×FS NORMAL, 512×FS NORMAL or a buffered, digital copy of the crystal oscillator signal to other ICs in the system."

    Version with buffered copy of the crystal oscillator isn't correct solution for configuration with ADAU1442/1445 working as master and ADAU1966 working as slave (without PLL circuit) because ADAU1966 need 512×FS in direct MCLK mode.

    It can be done with f_MCLK = 256×FS NORMAL and f_CLKOUT = 512*FS NORMAL. But f_CLKOUT > f_MCLK suggests that the PLL inside ADAU1442/1445 is in use:

    f_MCLK = 256×FS -> /4 = 64×FS (PLL DIVIDER) -> ×56 = 3584×FS (CORE CLOCK MULTIPLIER) -> /7 (???) = 512×FS = f_CLKOUT

    It is well known that analog PLL has poor jitter performance in low frequency region (f < 10 kHz).

    Perhaps, however, a solution with ADAU1966 operating as master is better ?

    I have two last questions:

    5) ADAU1966 accept f_MCLKI from 256×FS to 768×FS (FS=48kHz). Is it also true if I use internal oscillator, or similar to ADAU1442/1445 only 256×FS is acceptable ?

    6) I have a positive experience with AD1955 DAC where Data Direct Scrambling technology is implemented (where multibit nonlinearities are converted to upper frequency noise, in other DAW algoritms only to white noise).

    Does ADAU1966 also use DDS ?

    Regards

    Piotr Szymkowiak

Reply
  • Hi, Coleman

    Thank you with comprehensive answers to points from 1) to 3).

    But I still have doubts about the point 4). I have just read carefully the documentation of ADAU1442/1445 and there is written (page 21):

    "The on-board oscillator is designed to work with a 256×FS NORMAL master clock, which is 12.288 MHz when FS NORMAL is 48 kHz"

    "CLKOUT can output 256×FS NORMAL, 512×FS NORMAL or a buffered, digital copy of the crystal oscillator signal to other ICs in the system."

    Version with buffered copy of the crystal oscillator isn't correct solution for configuration with ADAU1442/1445 working as master and ADAU1966 working as slave (without PLL circuit) because ADAU1966 need 512×FS in direct MCLK mode.

    It can be done with f_MCLK = 256×FS NORMAL and f_CLKOUT = 512*FS NORMAL. But f_CLKOUT > f_MCLK suggests that the PLL inside ADAU1442/1445 is in use:

    f_MCLK = 256×FS -> /4 = 64×FS (PLL DIVIDER) -> ×56 = 3584×FS (CORE CLOCK MULTIPLIER) -> /7 (???) = 512×FS = f_CLKOUT

    It is well known that analog PLL has poor jitter performance in low frequency region (f < 10 kHz).

    Perhaps, however, a solution with ADAU1966 operating as master is better ?

    I have two last questions:

    5) ADAU1966 accept f_MCLKI from 256×FS to 768×FS (FS=48kHz). Is it also true if I use internal oscillator, or similar to ADAU1442/1445 only 256×FS is acceptable ?

    6) I have a positive experience with AD1955 DAC where Data Direct Scrambling technology is implemented (where multibit nonlinearities are converted to upper frequency noise, in other DAW algoritms only to white noise).

    Does ADAU1966 also use DDS ?

    Regards

    Piotr Szymkowiak

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