ADAU1966 - important questions

Hi,

I am going to connect ADAU1966 DAC and ADAU1442/1445 Sigma DSP together and I have some questions.

1) On page 15 of ADAU1966 documentation we can read:

"If the ADAU1966 is to be used in direct MCLK mode, the PLL can be powered down in the PDN_THRMSENS_CTRL_1 regiter. For direct MCLK mode, a 512 × FS (referenced to 48 kHz mode) master clock must be used as MCLK, and the CLK_SEL bit in the PLL_CLK_CTRL1 register must be set to b1."

But is it still needed circuit from Figure 8 (between LF and PLLVDD pin) ? Maybe LF and PLLVDD pin may be left unconnected or tied to ground ?

2) In the documentation is missing figure of the oscillator circuit similar to that can be found in the ADAU1442/1445 datasheets (Figure 9, page 21). I don't know for example if 100 ohm resistor serial with XTALO is necessary or not. I don't have information about load and stray capacitance, too.

3) I'm not sure if pins AVDD1 to AVDD4 are connected together inside the ADAU1966 or not ?

4) Which solution is better to get best audio performance (SRC inside ADAU1442/1445 will be enabled) ?

a) ADAU1966 MASTER, ADAU1442/1445 SLAVE

ADAU1966 LRCLK - OUT, ADAU1442/1445 LRCLK - IN

ADAU1966 MCLKO -> ADAU1442/1445 XTALI

b) ADAU1966 SLAVE, ADAU1442/1445 MASTER

ADAU1966 LRCLK - IN, ADAU1442/1445 LRCLK - OUT

ADAU1442/1445 CLKOUT -> ADAU1966 MCLKI

Regards,

Piotr Szymkowiak

  • 0
    •  Analog Employees 
    on May 2, 2012 11:28 PM

    Hi Piotr,

    Thank you for your interest in the ADAU1966 DAC.

    1) If you are not going to use the PLL, you may power it down using the appropriate register; in this case you do not need to supply the Loop Filter RC components. It is important that you still provide power to the PLLVDD pin, however.

    2) I apologize that there is no applications circuit for using the ADAU1966 with a crystal. The crystal loop port is identical to the port on the ADAU1442; please use the same circuit. The User Guide for the eval board will be posted soon, and many questions will be answered by the schematic of this board.

    3) The AVDDx pins are connected inside the ADAU1966, however in order to achieve the datasheet specified performance, it is necessary to decouple each pin individually with 0.1 µF in parallel with 10 µF. I would recommend running a 'starred' set of power traces from the supply to each AVDD pin.

    4) In the case that you are not using the PLL inside the ADAU1966, I would recommend that the ADAU1442 act as the Master, driving clocks and data into the ADAU1966. Proper termination of the clock and data lines is very important for good signal integrity, and will help keep any jitter issues to a minimum; this is important if you are not using the PLL.

    Best regards,

    Coleman

  • Hi, Coleman

    Thank you with comprehensive answers to points from 1) to 3).

    But I still have doubts about the point 4). I have just read carefully the documentation of ADAU1442/1445 and there is written (page 21):

    "The on-board oscillator is designed to work with a 256×FS NORMAL master clock, which is 12.288 MHz when FS NORMAL is 48 kHz"

    "CLKOUT can output 256×FS NORMAL, 512×FS NORMAL or a buffered, digital copy of the crystal oscillator signal to other ICs in the system."

    Version with buffered copy of the crystal oscillator isn't correct solution for configuration with ADAU1442/1445 working as master and ADAU1966 working as slave (without PLL circuit) because ADAU1966 need 512×FS in direct MCLK mode.

    It can be done with f_MCLK = 256×FS NORMAL and f_CLKOUT = 512*FS NORMAL. But f_CLKOUT > f_MCLK suggests that the PLL inside ADAU1442/1445 is in use:

    f_MCLK = 256×FS -> /4 = 64×FS (PLL DIVIDER) -> ×56 = 3584×FS (CORE CLOCK MULTIPLIER) -> /7 (???) = 512×FS = f_CLKOUT

    It is well known that analog PLL has poor jitter performance in low frequency region (f < 10 kHz).

    Perhaps, however, a solution with ADAU1966 operating as master is better ?

    I have two last questions:

    5) ADAU1966 accept f_MCLKI from 256×FS to 768×FS (FS=48kHz). Is it also true if I use internal oscillator, or similar to ADAU1442/1445 only 256×FS is acceptable ?

    6) I have a positive experience with AD1955 DAC where Data Direct Scrambling technology is implemented (where multibit nonlinearities are converted to upper frequency noise, in other DAW algoritms only to white noise).

    Does ADAU1966 also use DDS ?

    Regards

    Piotr Szymkowiak

  • 0
    •  Analog Employees 
    on May 4, 2012 1:19 AM

    Hi Piotr,

    Yes, you are correct that you must drive the ADAU1966 in 512xFs if you do not use the PLL. If I were designing the system, I would use the ADAU1966 as the Master, with an active PLL; the ADAU1966 would then be the master of the ADAU1442. There should be very little difference between the two architectures and I am not sure if one would be better; the ADAU1966 is very immune to jitter problems with the PLL active.

    5) When you say internal oscillator, do you mean crystal? The ADAU1966 can run in any of the MCLK rates with a crystal.

    6) The ADAU1966 uses data scrambling.

  • Hi Coleman,

    5) Yes, I mean crystal.

    Thanks for all answers.

    I have just started the project (ADAU1442 - slave, clocked from ADAU1966, ADAU1966 - master, 512 x FS from crystal, without PLL).

    Regards

    Piotr Szymkowiak

  • 0
    •  Analog Employees 
    on May 7, 2012 5:29 PM

    Hi Piotr,

    I look forward to hearing status reports as you move along.

    BR,

    Coleman