AD5791: Bad results for linearity measurement

Hi,

I am using a precision dac source circuit based on the AD5791 20 bit DAC. The problem faced by me is, while 1 LSB - max INL/DNL spec is guaranteed for the DAC including the recommended AD8676BRZ voltage reference buffers and AD8675ARZ output buffer, the linearity results obtained by me during measurement using agilent 3458A digital multimeter are very bad. To reduce test time, i had used a step size of 32, and done a measurement run across the full range, ie -10 to +10V, but the INL results obtained are exceeding 3 LSB, and this LSB is at 15 bit level, not 20 bit. So if we calculate at 20 bit level, results are much worse.

My DAC source uses a supply of +/- 14V, and uses the recommended AD8676BRZ voltage reference buffers and AD8675ARZ output buffer, and the buffered output is applied to an inverting adder using OPA1612 opamp, which is meant to add dc offset to the DAC output. The test was done at 0V DC offset. In the test, sufficient settling time has been given for the DAC output to settle( about 0.1ms). The INL plot acquired looks strange as well. Please find the following attachments

Attachments:

1.The schematic of the entire circuit: Page nos 6 and 8 depict the connections associated with the DAC part. Also the test was conducted with R75=50E( page no 8)

2.The INL-DNL plots obtained with stepsize of 32, and calculated with 15bit resolution LSB, (ie LSB=20/(2^15))

Thanks

Anoop

attachments.zip
  • 0
    •  Analog Employees 
    on May 23, 2012 2:57 PM

    Hi Anoop,

    The issue here is the voltage reference that is being used. It will not be possible to obtain 1LSB INL with the ADR01BRZ.

    An ultra-stable temperature controllable reference will be needed for this DAC to get the best performance achievable.

    The LTZ1000 could be an alternative in this case.

    Regards,

    Estibaliz

  • Hi Estibaliz,

    Thanks a lot for your prompt response. Could you give us a brief estimate of how much the performance of the DAC will be affected by using ADR01 reference, that is, an approximate idea of the max/min INL-DNL figures we can hope to achieve using ADR01, since we are into an advanced stage of the project, and it wont be too feasible for us to change to LTZ1000 at the moment. If we can get a rough idea of the baseline performance with ADR01 reference, we can set the specifications for the project likewise.

    Also, could you offer us a logical explanation for the particular shape of the INL curve attached to the previous mail? It seems to increase steadily till some voltage, then decreases, and when reverses with opposite polarity. Is this pattern of INL expected?

  • 0
    •  Analog Employees 
    on May 24, 2012 2:59 PM

    Hi Anoop,

    If we go back to the plots there is sign of much more noise at lower codes, which makes us look back at how the negative reference is generated.

    For the INL curve, that shape could be caused by DAC-code dependent currents getting onto the signal path for the reference. To debug this and see that dependence, a reference voltage at the AD5791 vs. code plot could be helpful.

    Looking at the -10V generated on page 6 of the schematics, being GND for U10 driven from the op amp U11, is that -10V reference a good quality signal?

    There are two options that would be recommended here:

    ·         Generate the -10V reference by inverting the +10V obtained from U7.

    ·         For a +/-10V output range, the gain of two configuration offers bipolar output span from a single ended reference input with VrefN=0V. http://www.analog.com/en/circuits-from-the-lab/CN0177/vc.html

    Regards,

    Estibaliz

  • Hi Estibaliz,

                            

    Sorry it is not clear from the schematic. Actually first for generating the negative reference, we had tried using an application circuit given in the ADR01 datasheet to generate negative reference. But later we learned from them that that circuit was non functional, and had been removed from the future datasheets. So in our actual configuration, U10 has been removed, and what we are actually doing is what u said exactly, we are inverting the +10V reference generated by U7 and inverting it using a very low noise OPA211 opamp at U11.Also, i don't feel using a gain of 2 configuration could be feasible at this stage, as the board is already done. So inverting ADR01 output, as we have done now, is good enough I hope? Anyway we will try to debug the reason for the INL curve shape as you said and get back to you. Thanks a lot.

    Thanks,

    Anoop

  • Hi Estibaliz,

    Just a doubt, in advance. Suppose  we DO find such an interdependence, ie, DAC-code dependent currents getting onto the signal path for the reference, is that actually expected to happen? since the references are buffered, ideally that shouldn't happen isn't it? Only the supply currents are supposed to be DAC dependent isn't it? Also, not sure if the 3458A digital multimeter has any role  in this (the INL curve shape) as well.  Anyway we will check as per your recommendation and get back.

    Thanks a lot

    Thanks,

    Anoop