I am working with a AD5449 DAC, interfaced with BF561 via SPORT1 on a custom board. I am facing an issue where the DAC fails to respond to the commands from the DSP.
Failure when power on reset is not applied to the DAC
void DacInit(void)
{
*pSPORT1_TCLKDIV = CLKDIV; // CLKDIV = 3: SCLK = 125MHz => SPORT1 TX CLK = 15.625MHz
*pSPORT1_TCR2 = SDLEN; // SDLEN = 16; DAC fails to respond with SDLEN = 15.
*pSPORT1_TCR1 = TFSR | ITFS | ITCLK | LTFS | LATFS | TSPEN;
/* CLR# would be previously high. Provide a high to low... to high transition */
ClrLow();
asm("nop;");
asm("nop;");
asm("nop;");
asm("nop;");
asm("nop;");
asm("nop;");
asm("nop;");
asm("nop;");
asm("nop;");
asm("nop;");
ClrHigh();
asm("nop;");
asm("nop;");
asm("nop;");
asm("nop;");
asm("nop;");
asm("nop;");
asm("nop;");
asm("nop;");
asm("nop;");
asm("nop;");
/* Default power on condition */
*pSPORT1_TX = 0x0000;
while(!(*pSPORT1_STAT & TXHRE));
asm("nop;");
asm("nop;");
asm("nop;");
/* Standalone mode */
*pSPORT1_TX = 0x9000;
while(!(*pSPORT1_STAT & TXHRE));
asm("nop;");
asm("nop;");
asm("nop;");
#define DAC_A 0x1000
#define DAC_B 0x4000
/* Load and update both DACs to midscale */
DacWrite(DAC_A, 0x800);
CoreaDelay(0x00FF);
DacWrite(DAC_B, 0x800);
CoreaDelay(0x00FF);
}
void DacWrite(u16 channelNo,u16 data)
{
u16 uiDACData = channelNo | data;
*pSPORT1_TX = uiDACData;
while(!(*pSPORT1_STAT & TXHRE));
}
Consider the following events,
1. Board is powered off
2. Power on board. DSP and DAC both receive a power on reset.
3. The output voltage of DAC is at 0V.
4. DSP initializes DAC and DAC responds well through out the session.
5. DSP resets, for example, due to a watchdog time out.
6. Output voltage of DAC remains as it was before Step 5.
7. DSP performs the same steps during initialization.
8. DAC does not respond to the commands.
Is there anything that I could do during the initialization sequence to may be bring the DAC to a condition it would be after power on reset? Any help is appreciated.
~Bharath
