AD5254 - I2C Interface Questions

     Good morning.  I have a customer that is going to interface with the AD5254 via a Xilinx Spartan-6 FPGA and he has a couple of questions.

     1)  In Figure 29 of the data sheet, it indicates that the slave is generating the stop condition when all of the other figures indicate that the master issues the stop condition as is usually the case with I2C?  Is the data sheet correct or is this a typo and the "P" box in Figure 29 should really be gray instead of white?

     2)  The customer wants to use the NOP command (Figure 31) to set the RDAC address from which he can the follow the NOP command with a current READ command (Figure 29).  As I read the data sheet and Figure 31, you can only set the three address bits in the NOP command to read EEMEM locations 0 thru 7.  However, the customer has downloaded a VHDL model for the AD5254 and his simulations are failing because the model is not behaving in this manner for the case where a NOP quick command is issued.  The model seems to keep two separate address registers - one for the normal command case and one for the quick commands.   So the address for the quick command was saved, but it was not transferred to the other address register that would be used on the next current read command.  Is this the correct operation or a flaw in the model?

     Thank you.

     Richard A. Pensabene


  • 0
    •  Analog Employees 
    on Nov 2, 2012 9:02 AM

    Hi Richard,

    1- You are right, the STOP condition is always generated by the master.

    2- Why you are using quick commands to set the register address? You should access as /REG.



  • 0
    •  Analog Employees 
    on Nov 2, 2012 1:04 PM

    Hi hawkfish,

    If you see table 7 and table 8, all the access to write/read, in this case to the EEPROM, are done accesing as /REG and not as CMD.



  • 0
    •  Analog Employees 
    on Nov 2, 2012 3:16 PM

    Hi Michael,

    You are right, the NACK and the STOP must be generated by the master.

    looks like figure 29 and figure 30 are both wrong.



  • Hi Miguel,

      I'm the customer that Rich is referring to.  The reason I chose to use the quick command is because the data sheet page 17 shows a dummy write operation with a quick command.  Figure 31.  As I thought about it a bit, I started to doubt that this is the correct technique...  And my doubts were reenforced with the failing of the model that I have downloaded... 

    So a dummy write is as shown in figure 30 not figure 31...  I think the "(Dummy Write)" text belongs on figure 30.

  • Miguel,

      I think I always understood that you need to perform /REG access especially for the writing.  However for the reading, it's all about understanding how to set the internal address registers (via Dummy Write).  When I read the text for Figure 31 "(Dummy Write)", I figured the device was just replacing the lower bits of the address in the internal address register.  Knowing that all I really need the device to do is to set A1 and A0 to read back one of the four RDAC values, I thought that I could exploit this.

    For my application, all I need to do is read back RDAC values, I never need to read back EEPROM locations.  So I figured I would exploit the Quick command version of "Dummy Write"... 

    From talking to you and my own experimentations....  I don't think there is a quick command (Dummy Write)..

    Just bad wording for Figure 31.

    Anyways, you already helped me.  I'm implementing the dummy write as shown in Figure 30 using /REG.

    Thanks for your help,