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Questions on SPI of AD5760

Hi all

This is my first time to build a four-layer board with a such high-precision DAC. I made the system and it does not work. I do not know what is wrong.

Could you please kindly help me to check the SPI?

Attached files are the timing diagram captured about CLK VS SDO; CLK VS SYNC*; CLK VS LATCH*.

I am trying to use the gain*2 mode.

The first SPI code is 0x200000, which is the configuration code.

The second SPI code is 0x1fff00, which is to write the DAC register and then the DAC will be latched.

Thank you very much.

Regards

Richie

spi_pics.rar.zip
  • Hi richiechen,

    First of all, have you been able to communicate with the DAC?.

    I assume you have not obtained any type of response from the part yet?

    The timing plots look good although I would suggest to check the following timing characteristics with Table 4 in the datasheet http://www.analog.com/static/imported-files/data_sheets/AD5760.pdf . Table 4 specifies the minimum amount of time between any changes on the lines, so those timings need to be carefully selected.

    - CLK vs Latch: (t12) LDAC pulse width low

    - CLK vs SYNC: (t4) SYNC to SCLK falling edge setup time

    For a gain of two mode, the control register is being well configured writing a 0x200000 code to it.

    Once the control register is configured the user can write to/ read from the part.

    Regards,

    Estibaliz

  • Hi Estibaliz

    Thanks for your help!!

    Problem solved.

    The timing diagram is correct. When I was trying to test the maximum and minimum value of DAC, I just used 0xffff and 0x0000 and expecting them to have minimum and maximum values.

    However 2's complement is adopted by DAC as a default value. As a result, there is no big difference between these two values. And I though I made s mistake on SPI.

    Now it works fine.

    Thank you very much!

    Regards

    Richie CHEN