I am connecting 3 AD5292's on one SPI channel. So SCLK, DIN, and SDO are all shared. The !SYNC pins are independently controlled. I know about the pull up resister on the SDO. I will only be talking to one chip at a time. I am worried about my master not being able to receive data from a SDO pin because of the other SDO pins on the channel. I know that the SDO pins need to be high impedance when not used. Will the chip put the SDO in high impedance when !SYNC is high, or do I have to do it?
page 25 says "To place the pin in high impedance and minimize the power dissipation when the pin is used, the 0x8001 data word followed by Command 0 should be sent to the part." Can you elaborate on this?
It took one of our engineers several days to find out some really bad things about the chip. The chips SPI interface is totally messed up in several ways:
1. Internal SDO pin implementation seams to be a total mess:
- One needs a 2.2 kOhm pull up to get a mediocre high output (Vcc-0.4V). Any larger value (e.g. 10k) does not give a high! You name it. There is a big problem inside the chip...
- still this 2.2k pull up does not save your usual shared SPI board design. Because daisy chaining is only nice in theory real world board designs typically connect all MOSI, MISO and CLK pins to one single microcrontroller's SPI port. Every SPI slave gets its own chip select signal. This allows you to write separate firmware modules to control each SPI hardware independently from each other. So you can handle several devices with different SPI schemes and data lengths with one SPI hardware module. In order to enable this each SPI slave needs to set its MISO to High Z if deselected via chip select signal. Not this potentiometer: you need to search in the Analog forums to find out what the data sheet is trying to hide and that the SDO pin only goes to High Z when you send two (2) strange commands (0x8001 and 0x0000) The first is completely out of the potentiometers command regime (data sheet states: "The 16-bit input word consists of two unused bits (set to 0)"). It looks like a hack or a debugging command, not build in intentionally.
- next funny thing is this: "it is important to power Vdd and Vss first before applying any voltage to Terminal A, Terminal B, and Terminal W. Otherwise, the diode is forward-biased such that V DD and V SS are powered up unintentionally...The ideal power-up sequence is GND, V SS , V LOGIC and V DD , the digital inputs, and then V A , V B , and V W ."
Most of us engineers find it totally ok to make mistakes. We all do it every day ourselves. It seams natural to us too that one don't want to fix all problems of a chip if there exist workarounds. Chip revisions are expensive. Like if you messed up the SPI totally but you can fix its bad behaviour by adding a strong resistor and sending some hack commands for High Z mode. Just note it honestly and clearly in the data sheet and in the reference design.
But we all get totally frustrated, when someone claims to be the "World leader in high performance signal processing", messes a simple digital potentiometer design totally up, tries to sweep the problems under the carpet. And we the engineers are loosing hours our even days for finding all that stuff out the hard way.
engineer12 said:- One needs a 2.2 kOhm pull up to get a mediocre high output (Vcc-0.4V). Any larger value (e.g. 10k) does not give a high! You name it. There is a big problem inside the chip...
Could anyone comment on this?
If the leakage current is max. 1µA, as stated in the datasheet, even with 100k the high output should be max. 0.1V below Vlogic.
Please raise your query in a separate thread..