I am designing a multi-channel DAS. The specificatios or as given below;
Total channels : 24
Analog input signal range : +/- 10V
Resolution of ADC : 16 bit
Gain error : <= 0.02% of FSR i.e <=4mV
Offset voltage : +/-1.2mV
Temperature : 25 DegC to 45 DegC
I am using the following architecture;
Input ==> Filter ==> MUX(ADG1207) ==> IA(AD8421) ==> ADC(AD7663)
My analysis shows that meeting above mentioned gain error specification is not possible without any calibration. It is because the instrumentation amplifier itself has a typical gain error of minimum 0.01% . In addition to that ADC has its own gain error. So, we thought of calibrating our system in following manner.
1. Offset voltage in a signal path can be found by connecting the differential inputs to a known reference.
2. Gain error correction demands a known reference to do so. Since high precision(>=18bit) DAC is costly, I thought of using a calibration technique as given in the document. Let me briefly explain the procedure.
a. Get a low precision DAC. ( say 4 bits)
b. Get a high precision ADC i.e >= 20 bits. ( high precision & low frequency ADC is little cheap compare to high precision DAC )
c. Use the high precision ADC as a digital voltmeter to measure the output of low precision DAC. Keep the reading in FPGA.
d. Now, give the same input to our DAS. Capture the output of DAS and store it in FPGA.
e. Repeat the steps c & d for different voltage levels of low precision DAC. (if DAC is 4 bits - 16 voltage levels)
f. Now we can plot input Vs output. [ Input - High precision ADC output; Output - Designed DAS output ]
g. From the above plot we can find out the gain error slope.
h. Since the gain error is measured through calibration, necessary correction can be made during actual functioning.
I have following concerns about this method.
1. Is it practically reliable solution.
2. If so, how much gain error can I tolerate.
Please suggest some other well known or reliable method of calibration.
Note: Calibration should be done on board and should not be a manual correction.
We are looking into this, we'll get back to you.
It appears that your suggest calibration method could work in theory, but you have to verify it on your end and it may be complicated given that each gain block will add additional gain error and extra components on your board. Therefore, I’d suggest you to use a 20-bit precision DAC instead to ensure you meet the external calibration requirements for your DAS. Let us know if you have any specific question about ADI part.
Thanks for your reply.
I believe that you are talking about the gain blocks used in between calibration DAC and ADC. It was just a conceptual block diagram.
Actually, we can remove those gain blocks, if the calibration DAC is capable of giving +/-10V output. Even though the output of DAC is not precise I can read the exact value at the output of DAC through Calibration ADC. Since the same input is fed into our DAS system, the error value is calculated by subtracting DAS output from Calibration ADC output. So, with respect to the input the calculated error is correct. Now, I am segregating these errors for different levels of calibration. For example with 8 bit DAC, I get 256 error co-efficient corresponds to 256 voltage levels. If the total voltage range is 20V, then for each 78.125mV range I will have an error coefficient.
It is always assumed that the gain error is linearly increasing from lower voltage to higher voltage. If total gain error in signal path is 0.1%( 20mV, if 20V dynamic range is assumed) then gain error is zero at -10V and 20mV at +10V. Practically it is not so, gain error is not so linear as we assumed. So, by segregating the total voltage range into 256 levels (say) actually reduces the error significantly.
Please give your comments.
I have moved this discussion over to Precision DACs community. Someone here should be able to answer your query.