I had a question on AD5111 shutdown mode which is described in datasheet page 18 (Rev.B) as follows.
The AD5111/AD5113/AD5115 return the wiper to prior shutdown position if any other operation is performed.
Q-1) What is the meaning of "prior shutdown" ?
Is it indicating prior occurence of "shutdown command" which is described in same paragraph ?
Or it is including some other cases, example, unintended supplied power down ?
Q-2) I assume it means AD5111 is storing the wiper position when prior "shutdown(which of Q-1)" maybe in EEPROM.
Is it separate from the value which is stored by EEPROM Write Operation ?
Q-3) It may be a same question as Q-1, but if unintended power down occurs when operating in position 100, for example, and EEPROM is holding position 50 written by prior write operation, what is the position value it will start at next re-starting ?
Sorry for these fundamentals, but your helps would be very much appreciated.
Thank you very much for your reply.
Regarding to 1, shutdown command disconnect terminal A from W. Why this improve signal attenuation in W, when disconnect A source signal ? Sorry to this basic question, but could you please provide any sample schematic and explain ?
A terminal is disconnected from the string resistor,
the maximum attenuation that you can achieve at zero code is -50dB,
In shutdown mode -60dB,
We had understood teminal A is disconnected when Shutdown. What we do NOT understand is reason why it result to improve signal attenuation at audio application.
I found Audio Volume Control with Zipper Noise reduction in the datasheet of AD7376 page.17 Figure 35. It control CS signal when zero-crossing.
Are you talking about these type of control improve signal attenuation ? If so, how shutdown function is working in it ? (Figure 35 and related description does NOT mention to shutdown.)
Thank you very much for all of your answers.
Sorry to say, but I have one more question.
Please see attached chart. In past answer of this thread, you answered for B, U/D hold time is 20ns (Vdd >2.7V) to 40ns (Vdd < 2.7V).
How about A, (U/D setup time for CLK) has to be ?