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AD5111, shutdown mode



I had a question on AD5111 shutdown mode which is described in datasheet page 18 (Rev.B) as follows.


The AD5111/AD5113/AD5115 return the wiper to prior shutdown position if any other operation is performed.


Q-1) What is the meaning of "prior shutdown" ?

Is it indicating prior occurence of "shutdown command" which is described in same paragraph ?

Or it is including some other cases, example, unintended supplied power down ?


Q-2) I assume it means AD5111 is storing the wiper position when prior "shutdown(which of Q-1)"  maybe in EEPROM.

Is it separate from the value which is stored by EEPROM Write Operation ?


Q-3) It may be a same question as Q-1, but if unintended power down occurs when operating in position 100, for example, and EEPROM is holding position 50 written by prior write operation, what is the position value it will start at next re-starting ?


Sorry for these fundamentals, but your helps would be very much appreciated.


Best Regards, 

  • Hi,

    If RDAC = 12, you place a shutdown command, terminal A will be disconnected.

    A new command will exit from shutdown, loading RDAC = 12 and connecting again terminal A to teh string resistor.

    The part store the RDAC value is a intermediate volatile register.

    If the supply is disconnected, once the part is powered again, the POR circuit will restore the value stored into the EEPROM to the RDAC register.



  • Hi,

    Thank you for your reply.

    Please let me confirm as follows, and please remedy if wrong.

    1) Shutdown is not indicating power down. It is indicating intentional cutoff of terminal-A during power is still on, which is controlled by shutdown command from external.

    2) RDAC value is never be stored into EEPROM unless write command is effective.

    3) RDAC register is volatile and must be lost if sudden unintended power down occurs.

    Sorry for these fundamentals again, and your confirmation would help us to understand the parts.

    Best Regards,

  • Hi,

    Thank you for your clarifications.

    Sorry to say, please let me add additional questions.

    1) Sorry to this fundamentals, but what is the purpose/application of this shutdown mode, are you assuming ?

    Is this a kind of switch to switch over between A-W and W-B when potentiometer, or connect/disconnect between 2 terminals when rheostat ?

    2) When EEPROM write operation, datasheet describes <The write cycle is started by applying a pulse in the U/D pin when CS is enabled and CLK remains high, as shown in Figure 3.>

    Here it is said CLK pin must remains high but how long it remains high ?  t6 is described as <CS rise to CLK hold time> but Figure 3. seems doesn't matter to CLK.

    Could you please clarify how CLK should be in this case ?

    Best Regards,

  • 1- Improve signal attenuation in the W pin from A source signal, ie audio applications.

    2- You are right, description is incorrect. t6 does not apply for this command. In this case, the description must say, U/D hold time 20ns (Vdd >2.7V) to 40ns (Vdd < 2.7V)

    Best Regards,


  • Hi,

    Thank you very much for your reply.

    Regarding to 1, shutdown command disconnect terminal A from W. Why this improve signal attenuation in W, when disconnect A source signal ? Sorry to this basic question, but could you please provide any sample schematic and explain ?

    Best Regards,

  • Hi,

    A terminal is disconnected from the string resistor,



  • the maximum attenuation that you can achieve at zero code is -50dB,

    In shutdown mode -60dB,



  • Hi Miguel,

    We had understood teminal A is disconnected when Shutdown. What we do NOT understand is reason why it result to improve signal attenuation at audio application.

    I found Audio Volume Control with Zipper Noise reduction in the datasheet of AD7376 page.17 Figure 35. It control CS signal when zero-crossing.

    Are you talking about these type of control improve signal attenuation ? If so, how shutdown function is working in it ? (Figure 35 and related description does NOT mention to shutdown.)

    Best Regards,

  • Hi,

    Thank you very much for all of your answers.

    Sorry to say, but I have one more question.

    Please see attached chart. In past answer of this thread, you answered for B, U/D hold time is 20ns (Vdd >2.7V) to 40ns (Vdd < 2.7V).

    How about A, (U/D setup time for CLK) has to be ?

    Best Regards