AD5621 Offset Voltage

Hi Robert,

Offset error depends on temperature and supply voltage.

See figure 28 and 36 for more details.

Regards,

Miguel

Hi Miguel,

Thank you for the fast reply.

Correct, figure 28 shows offset error versus temperature.

Anyway the maximum value in this chart is 1.2mV @ 120°C and Vdd = 5V.

The specification on page 3 states 10mV as maximum.

What other conditions can make the offset go up to 10mV?

Regards

Robert

Hi,

there is also a contradiction for the typical offset values @ 25°C:

-) Table 2:      0.063 mV

-) Figure 30:   around 0.8 mV

Hi Reinhard,

The data from spec table comes from Yield Analise, that analyzed hundreds of samples form different wafers.

The plots come from a single device that may or maybe not fit within typical distribution.

Regards,

Miguel

Hi Miguel,

I understand, but still I am surprised of the huge variation between typical and maximum values.

From my experience typical and maximum values have a ratio of approx. 1:2 to 1:10.

In this case we have a ratio of 1:160!

That means we have to do our own binning before the device gets assembed onto the board.

Could you indicate a ratio of how many devices out of 100 or 1000 pcs might have such a high offset voltage?

Regards,

Robert

Hi Harry,

Thanks for your comment.

I believe we have to follow the recommendation in your last sentence.

Robert