One of my customer builds his prototype board using AD5668 DAC, and its output goes to zero occasionally.
During his fixing work, one question comes up as next;
Powered up his board, at Vdd=5V, Vref=Vdd.
/SYNC, DIN, SCLK terminal voltages are logic low, and /LDAC, /CLR terminal is logic high.
Analog output is 2.5V (mid scale).
Next step, /CLR goes to low.
He would like to confirm that the analog output should goes to zero or should stay 2.5V or else?
He understand that this condition is not normal, however he would like to know it in order for find a clue to his problem.
Based on the given data, the customer is using AD5668-3 (Power-On Reset to Midscale Code). The /CLR pin is falling-edge sensitive. Bringing the /CLR line low clears the contents of the input register and the DAC registers to the data contained in the user-configurable /CLR register and sets the analog outputs accordingly. The clear code values are user-programmable by setting two bits, Bit DB1 and Bit DB0, in the /CLR control register. The default settings clears the outputs to 0V.
Thank you for your quick reply.
I will talk to my customer based on your reply.
Thank you again for your help.