I am using a DAC8412B in an application and I want to understand if there are any restrictions or guidelines with regards to power up sequence. I don’t see anything related to power up sequence noted in the datasheet, but comparing the possible power combinations during power up with the absolute maximum ratings leaves me scratching my head.
Here are my circuit power conditions:
Vss: -15V standalone supply
Vdd: +15V standalone supply
Vlogic: +5V standalone supply
VREFH: +10V from an AD688 precision reference (the AD688 is powered from the same +/- 15V as the DAC8412B)
VREFL: -10V from an AD688 precision reference (the AD688 is powered from the same +/- 15V as the DAC8412B)
Since Vdd, Vss, and Vlogic are all powered from standalone supplies they can come up at different times, and the amount of time between when they all come up can vary by as much as ~10 ms. VREFH and VREFL can lag Vdd and Vss by as much as ~100 ms.
The reason I’m concerned is that walking through the different power up scenarios (i.e. Vdd = 15V, Vss = 0V, Vlogic = 0V, etc…) some of the absolute maximum ratings can potentially be violated, if I’m interpreting them right. For example:
Vdd can come up to +15V while Vss, VREFH, and VREFL are all still at 0V. This puts Vss to VREFL at 0V, which appears to violate the absolute maximum rating of -0.3V to +Vss-2.0V (0-2.0V=-2.0V).
Vss can come up to -15V while Vdd, VREFH, and VREFL are all still at 0V. This puts VREFH to Vdd at 0V, which appears to violate the absolute maximum rating of +2.0V to +33.0V.
Are there any concerns with the various power supplies coming up at different times in general and with the scenarios above specifically? Or might I be misinterpreting the absolute maximum ratings? I’m not concerned with functionality of the DAC during power up, I just want to make sure I don’t stress the part over time. Any help provided is greatly appreciated!
Thanks,
Zach
