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AD5429 PGA circuit problem

I have designed a two channel programmable gain control circuit using an AD5429 dual DAC.  The circuit is based on the recommended circuit shown in Figure 42 (Page 18) of the Rev E (latest) data sheet with the exception that the O2 pin is biased to +2.5V.  The actual circuit is shown in the attached PDF file.  The circuit is constructed on a 0.7 mm thick four layer PCB with the AGND layer immediately below the component side.  The PCB is 35 x 35 mm.  The commands sent to the DAC after power on are 0x9000 to set standalone mode, then 0x1FF0 to set DAC A to 255 then 0x4FF0 to set DAC B to 255.  VI is fed from a shorting jumper or a low impedance source.  Originally there was a 15 pF cap between O1 and RFB but removing this had no affect on VO and was deleted.  Both IC VDD pins are bypassed to AGND with 100 nF caps.  VR is generated from an REF3025 IC and is bypassed to AGND with a 1.0 uF cap.

 

My problems are as follows.

 

1)  With VI shorted, VO = 2.5 V superimposed with a 0.5-0.6V p-p very noisy 60Hz triangle wave.

 

2)  Placing a finger lightly on top of the AD5429 case increases the amplitude of the 60 Hz noise.

 

3)  With D = 0 and VI = 0.8, VO = 2.5V as expectd.

 

4)  With D = 128 and VI = 0.8, VO = 1.96V indicating an overall gain of -0.675 rather than -19.2.

 

5)  With D = 255 and VI = 0.8, VO = 1.53V indicating an overall gain of -1.21 rather than -38.25.  In addition the gain is not linear as a function of D.

 

Can anyone provide some insight as to what is causing the noise and what is causing the unexpected circuit gain?

Gain_control_circuit_01.pdf
  • Hi,

    If it is 60Hz noise is getting into your signal, that is usually related to grounding issues of the system as a whole. The DAC should have ample supply bypassing of 10 µF in parallel with 0.1 µF (you have this as the 100nF caps) on the supply, located as close as possible to the package, ideally right up against the device. You may refer to the PCB LAYOUT AND POWER SUPPLY DECOUPLING section in the data sheet for additional information.

    As for the gain, I have a couple of questions:

    • What is expected output voltage range?
    • What gain are you expecting? Based on the computation, you are expecting a gain of 38.4. Is this correct?
    • Your VI in your diagram is only from 0 to 0.06 but is in series with VR which would have an effective 2.5V to 2.56V seen in the VREF pin. Is this correct?

    Regards,

    Mark

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