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Is it ok to put capacitors on the AD5686R reference output?

The AD5686R has a very nice internal reference that I want to use as a reference throughout my board. This includes a SAR ADC which recommends a 1µF ceramic on its Ref input, to absorb the fast transients created during conversion. However, I don't know from the datasheet whether it's OK to have a large capacitive load on the Ref output of the AD5686R.

Is there some implicit assumption that a reference output can be used this way, or should I be concerned about the reference buffer becoming unstable?

  • Hi,

    From the AD5686R's point of view, you should just take note of the parameters that the internal reference could provide. Take note that the output current load capability of the reference pin is typically 5mA.

    On SARs that require an external reference, the reference input is a switched capacitor that consumes charge current during the SAR conversion bit trials. This can be a significant source of power consumption, depending on the ADC throughput rate and size of the internal capacitor DAC. The higher the ADC throughput, the more conversion bit trials (charging of caps), and therefore, more current is consumed in the capacitive DAC array. [1]

    Assuming you will be consuming 10mW for the ADC reference, that will still give you 4mA current load which is still within the specifications. I think you should be fine.

    Regards,

    Mark

  • Hi All,

    You can place up to 1uF cap before the opmap gets unstable.

    In fact, I recommend to place a 10nF cap even if the internal reference is used internally only.

    Regards,

    Miguel

  • Hi Mark, thank you for your answer.

    I estimate that the ADC Ref input will take less than 100µA, so this should not be a problem.

    I was more concerned about having a large capacitor at the buffered ref output, because I know that it's usually a bad idea to put a random capacitor directly at the output of a random op amp. However, I found the evaluation board schematics now, and it looks like that actually has 10µF tantalum in parallel to 100nF ceramic at the ref pin, so I am guessing that 1µF ceramic will also work fine - however, it's not a guarantee.

    Regards,

    Simeon

  • Thanks Miguel, I didn't see your answer when I posted before.

    How does the 1µF limit apply to the 10µF tantalum that is used on the evaluation board? Is that already on the "other side" of the stability limit, e.g. so large (and with sufficient ESR) that the op amp is stable again?

    So far I'd keep the 1µF, but I'm slightly concerned because it is at the limit of your figure. Should I rather reduce it a bit to e.g. 470nF, or maybe add a resistor in series with the capacitor?

    Regards,

    Simeon

  • Hi Simeon,

    10uF is far too large... I check the schematics for the EVB and you are right... we are populating 10uF which is not recommended... I'll ask what is physically the cap populated and I'll edit the UG and EVB to fix the problem.

    As I said, around 1uF should be good enough... .

    Say that, if you are planning to use this as a system reference, I'll recommend to place a 10nF cap close to the ADC reference... making sure that the  cap connected to Vref pins + teh caps connected close to the other component reference does not exceed 1.5uF.

    Regards,

    Miguel

  • Once more, thank you for clearing this up. I am now a lot more confident that my design will work well.

    Regards

    Simeon