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AD5698R READ OPERATION

Hello,

My customer is confused about AD5698R READ OPERATION.

Is it possible for you to confirm the I2C Read Operation timing?

Please find attached file. These are I2C timing chart.

As I pointed out, there are "ACK. BY Master" and the other. Compared with AD5698 and AD5698R. It seems different each other.

The customer is afraid of its typo.

Regards,

AD5698.pptx

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  • Hi Mark-san,

    I would like to confirm a thing. Is it possible for you to check?

    I think CPU should be master, DAC should be slave.

    During READ OPERATION, master and slave are changed.

    According to the timing chart of P22 on the datasheet of AD5694R,

    Start is Master, All of the ACK are master,

    Repeated start is Master, Stop is also master.

    At least, Ack should be supported by receiver for data transmitter.

       Phase                       Data Tramsmitted By    ACK Trasmitted By

       Start                       CPU            -

       FRAME 1 SLAVE ADDRESS               CPU         AD5696?

       FRAME 2 COMMAND BYTE                CPU            AD5696?

       FRAME 3 SLAVE ADDRESS               CPU?           AD5696?

       FRAME 4 MOST SIGNIFICANTDATA BYTE n        AD5696?          CPU?

       FRAME 5 SLAVE ADDRESS SIGNIFICANT DATA BYTE n   AD5696?          CPU?

       FRAME 6 MOST SIGNIFICANTDATA BYTE n – 1      AD596?          CPU?

       Stop                        CPU             -

    On the timing chart, which output Ack from CPU or AD5696R?

    How does customer set for "FRAME 2 COMMAND BYTE"?

    It seems to set internal pointer. But we couldn't find out format.


    FRAME4(MSB) and FRAME6(LSB) are data?


    Does FRAME 5 show address?

    Should the customer confirm it same as FRAME3?

    Regards,

Reply
  • Hi Mark-san,

    I would like to confirm a thing. Is it possible for you to check?

    I think CPU should be master, DAC should be slave.

    During READ OPERATION, master and slave are changed.

    According to the timing chart of P22 on the datasheet of AD5694R,

    Start is Master, All of the ACK are master,

    Repeated start is Master, Stop is also master.

    At least, Ack should be supported by receiver for data transmitter.

       Phase                       Data Tramsmitted By    ACK Trasmitted By

       Start                       CPU            -

       FRAME 1 SLAVE ADDRESS               CPU         AD5696?

       FRAME 2 COMMAND BYTE                CPU            AD5696?

       FRAME 3 SLAVE ADDRESS               CPU?           AD5696?

       FRAME 4 MOST SIGNIFICANTDATA BYTE n        AD5696?          CPU?

       FRAME 5 SLAVE ADDRESS SIGNIFICANT DATA BYTE n   AD5696?          CPU?

       FRAME 6 MOST SIGNIFICANTDATA BYTE n – 1      AD596?          CPU?

       Stop                        CPU             -

    On the timing chart, which output Ack from CPU or AD5696R?

    How does customer set for "FRAME 2 COMMAND BYTE"?

    It seems to set internal pointer. But we couldn't find out format.


    FRAME4(MSB) and FRAME6(LSB) are data?


    Does FRAME 5 show address?

    Should the customer confirm it same as FRAME3?

    Regards,

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