AD5781 Readback mode

Hi Terumasa-san,

The timing diagram that you attached is Figure 3 which is the Readback Mode Timing Diagram. In this case, the minimum SCLK cycle time for t1 is 60ns.

Regards,

Mark

Hi Terumasa-san,

When performing a write command, the part will mostly use buffers to drive the SDI pin. On the other hand, when data is being read from the SDO pin, the data goes through the SDO circuitry which incurs unavoidable delays. The minimum amount of time needed to be able to do a read increases because of this.

I hope I answered your question. Please let me know if you have any further questions.

Regards,

Mark

Hi Mark-san,

Thank you for your answer.

I have additional one question.

Though  I see that first 24 bit SDIN (red circle of attachment )  is the same operation in both write mode and readback mode ,
why is minimum SCLK cycle time differed ?

If possible, could you give me your advice about it reason ?

Regards,

Terumasa

Hello Mark,

Thank you for your asnwer.

Regards,

Terumasa