AD5592R DAC output limit

Pretty much know the answer, but I’ll ask anyway since the datasheet implies otherwise.

First use of the AD5592R with one DAC output, two A/D inputs, and one GPIO used.

Operating it at 3.3v since the SPI I/O coming from SN65LVDT41/14 LVDS SPI datalink devices.

 

 

Vref at 2.5 internal, set to 2x, wanted to get up to 4.1v out, but it stops at 3.3v.

This is covered nowhere in the datasheet that I see. Please correct me if wrong.

 

I could power this at 5v, but then it would violate the SPI high voltage logic level (>3.5v), which is why I guess the R-1 part is around, but didn’t like the pinout as much.

 

Anything I’m missing ?

 

Other than that, appears fine, SPI link running at 12Mbps which is the most I can do with this 3.3V processor.

Thanks

  • I ran into this as well. The output voltage can not exceed VDD.... actually, if you have a load, the limit is VDD minus some. Some of the package options allow you to have a Vlogic reference so that you can use 3.3V logic level, but then provide a 5V Vref if you want wider range on the IO pins. In that case, VDD needs to be at least your Vref. In my case I'm using it with a Raspberry Pi which has 5V available, but the serial interface is 3.3V. So I give VDD and Vref 5V and connect Vlogic to 3.3V. I'm using the 16-Lead LFCSP package option which allows this.

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    •  Analog Employees 
    on Aug 2, 2018 3:13 PM
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