I am working with DAC ADAU1966a and I am trying to do it work in mode STANDALONE but I am not getting it.
I am working with the next standalone setting:
Pin 46 - Set to 1 Standalone mode enabled (3,3V)
Pin 42 - Set to 1 Slave serial audio interface (3,3V)
Pin 43 - Set to 0 256 × fS (0V)
Pin 44 - Set to 0 (0V)
Pin 45 - Set to 0 I2S mode (0V)
I am using the internal regulator driver on board getting 2.5V from the 3.3V provided for my board. The regulator is working and the signal is clear and stable so looks working fine. I am using the recommended circuit on datasheet for this point.
I am feeding the analog power (IOVDDs) pins with the 3.3V and the digital pins (DVDDs) with the 2.5V provided for internal regulator. Pins AGND and DGND are connected to their respective GND.
Pin 17 MCLKI/XTALI: Asserting the PU/RST pin high, I driving a 12,228Mhz sourced from a FPGA getting a buffered version of this in the the MCLKO pin.
Pin 27 DBCLK: I am providing this clock from the FPGA with frequency 3,072Mhz. 64 cycles of this clock each DLRCLK cycle.
Pin 28 DLRCLK: I am providing this clock from the FPGA with frequency 48Khz.
Both (27 and 28) are synchronised and looks coherent.
Pin LF is unconnected, PLVDD is fed to 2,5V and PLLGND to GND.
PINs DSDATA: I am providing databits 1 delay DBCLK cycle upon DLRCLK changes. I2S mode. Latching data is on rise edge DBCLK so looks fine.
I am providing different 24 bits data: all zeros, all ones on each DAC but on the DACs outputs i am getting around 1,46V and not the expected data inputs.
I would be very grateful if you could help me with this matter and give some tip or help to solve the problem.