Time chart about AD5302 DAC

Hi Miguel,

>Customer bring SYNC low and transfer 16 clocks, right?

Yes

>SYNC is bring high again sometime later, right?

Yes,but it needs a long time. It means that t7 is a few seconds eg;.

>there are no extra clocks generated in the SCLK clock between last 16th pulse and SYNC falling edge, right?

SCLK is still sent in continuously not extra clock generate.

In other words, is your internal register overwrote after last DB0?

DB15 to DB0 are sent out continuously from forward circuit.

Thanks Kaos

Hi Kaos,

Im not fully understand the problem...

Customer bring SYNC low and transfer 16 clocks, right?

SYNC is bring high again sometime later, right?

there are no extra clocks generated in the SCLK clock between last 16th pulse and SYNC falling edge, right?

Regards,

Miguel

Hi Miguel,

Here is additional question from customer.

If /LDAC is fixed to L(connect to GND), then can your AD5302 update the register?

Your datasheet page-5 said as following.

"Pulsing LDAC low allows either or both DAC registers to be updated if the input registers have new data."

Does this mean to need min 20nsec Low pulse?

Thanks Kaos

Hi Kaos,

I guess your question is, when the DAC decodes the command, after the last 16th clock, or bringing SYNC high, right?

As far as the Ds states,

1- teh command is decoded bringing SYNC high.

2- If more than 16th clocks are generated, the part ignores the extra clocks

If LDAC is pull low, any update on the sift register will be immediately transfer to the DAC register.

Regards,

Miguel