ADAU1966 Evaluation board PLL not working

Hello,

                   I brought ADAU1966 evaluation board. I am using ARWB software with I2C to communicate with board. I was able to read and write to registers successfully. Initially I programmed all registers to reset state. then I made power up bit 1 in PLL_CLK_CTRL0 register that is  programmed to 01. I have given oscillator as clock source. I am able to see clock at TP20 clk_out point. But I am not getting master clock at MCLK pin in JP2 (Figure 14 in evaluation board user guide). Why is this happening??

                    Actually I wanted to use board with my clocks and DAC inputs (not for audio stream). So I was doing this. Do I have to program any other register to get the MCLK for loop filter.

With Regards

Shalini

  • 0
    •  Analog Employees 
    on Mar 22, 2016 5:54 PM

    Hello Shalini,

    Does your evaluation board exactly match up to what you see in the user guide? You may have a newer evaluation board and be using the older revision of the user guide. It is in the process of being updated but I could provide you with a copy.

    So send a picture of the board and also so I can see the jumper settings and see the revision.

    So you want the DAC board to be a slave to your LRCLK, BCLK and MCLK correct?

    I did not understand your comment about "(not for audio stream)"? Do you mean you want to send the data in I2S format rather than TDM format?

    The default for PLL_CLK_CTRL0 register is to use the MCLKIN pin to drive the PLL input. The loop filter for MCLK is a setting on the evaluation board so you have an option of using MCLK or LRCLK for the PLL.

    How are you planning on clocks and data to the evaluation board? Are you using a second evaluation board or is this your own hardware?

    Dave T

  • Hello,

                            I have downloaded the user guide of evaluation board from your site. I will surely sent you the photo as soon as I reach office next day.

                            I want DAC board to be slave for my LRCLK, BCLK and MCLK  that will be driven from FPGA. 'Not for audiostream' means I am neither using SPDIF or SDP to give input. I am driving eight channels of input from FPGA to the middle pins of jumper JP13 to JP20. Also I am using middle pins of JP10 AND JP20 to drive LRCLK and DBCLK driven by FPGA. I am planning to use I2S and drive all these pins mentioned above other than using as jumpers.

                            

                             When using Loop filter with MCLK ,I believe we have to short the JP2 jumper middle and left pin . When I tried to see clock in oscilloscope from the left pin I dont get any signal. That's what I queried about.

    With Regards

    Shalini

  • Hello Dave,

                  I am sending you the pics of board now. The Pic_showing jumper shows the one I have been talking about circled in red. I am asking if pin 1 in circle is supposed to get MCLK.

  • 0
    •  Analog Employees 
    on Mar 24, 2016 6:49 PM

    Thanks Shalini,

    Sorry for the delay. I was working on this response but kept getting interrupted, then I forgot about the site upgrade so that put an end to my posting this yesterday! Sorry about that!

    The pictures helped a lot. The good news is the version of evaluation board you have does match the user guide that is on the web.

    So your answer about JP2 is that you do have to insert the jumper between pins 1 and 2 to connect the proper loop filter to the LF pin. The signal on the LF pin is mostly a DC signal and it is the loop filter. Do not insert MCLK into this pin and you will not see when viewing on a scope. In fact, do not leave a scope on this pin because the capacitance of the probe can cause issues so I only look at it when it is required.

    The best place to insert MCLK is using J4 and then setting the jumper on J5 to the SMA position. However, it is difficult to find the mating connector for this SMA style of jack. So if that is true then just remove the jumper on J5 and inject MCLK on any of the four pins on the right side of J5. As it is seen on your pictures. All four pins are connected together.

    In your earlier post you mentioned connecting LRCLK and BCLK to the middle pins of JP10 and JP20. I think this was a typo and you meant to say JP10 and JP12. In that case you are correct, that is where you would connect those clocks.

    Now the problem with all this is that there is not a ground pin next to these jumpers. So it makes keeping a decent signal integrity more of an effort. You will need to connect a ground between the two boards you are using. I also try to twist a ground wire with these clock signals if possible. Keep the wires as short as you can. If you try to run at 192kHz fs you might have some difficulties keeping small pops and clicks out of the audio. At least this is my experience doing this in the lab.

    Let me know if you get it going.

    Thanks,

    Dave T

  • Hello Dave,

                   I think you have not understood my query completely. As you have mentioned I have connected my MCLK in right side pins of J5 after removing header. And of course I connected LRCLK and BCLK to the middle pins of JP10 and JP12 , mention as JP20 was my fault. After my connections I did not get output signal. So while debugging I doubted if my PLL is functioning properly. Then I probed on pin1 in JP2 (red circled jumper ) and expected to see clock signal I gave (and indeed saw on TP20) there also. But I am getting no signal there. I have kept all register settings to default value in IC data sheet. This is my problem. Any suggestion on this is welcome.

                I connected GND of my board to TP45 GND on ADAU1966 board. Sorry but I couldn't understand what you meant by " I also try to twist a ground wire with these clock signals if possible. Keep the wires as short as you can " . where more should I connect grounds to?

    With Regards

    Shalini