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AD1934 interface with Microcontroller - Not able to hear anything on DAC output


I'm interfacing the AD1934 DAC to an MCU's SPI interface. I have connected a 12.288MHz external clock signal to the MCLKI pin and left MCLKO pin as open.

Following are the AD1934's register configuration.

DAC Control 1 --> 0x60

DAC Control 2 --> 0x18

PLL and Clock Control 0 --> 0x98

DAC individual channel mutes --> 0x00

I have read back the registers what i have written and its the same what i have transferred.

I have also probed the LR Clock, Data and Bit clock lines and everything seems to be fine. But I cannot hear anything on the DAC output.

The audio data is a 16-bit signed LE with 48kHz sample rate. I have extracted the samples from .wav file and stored it in a C array format using a python script and used it in my code.

In some other post I've read that the data size is always 32-bit for AD1934. I have configured my master accordingly but no audio is coming out.

My MCU master uses the bit clock from AD1934 and generates the LR clock and data to be input to the AD1934.

Am i missing anything?



  • Hello Tri,

    This is a bit of an usual way to run the part. To have the BCLK be a master and the LRCLK a slave. I don't know if I have ever tried that personally. I think it will work. You may have to change the latch the data at the end of the cycle instead of the middle if you have some delay between the data edges from the BCLK edges.

    You did not send over the value of the DAC Control 0 register. This is important to see the entire format you are using.

    I see you set the DAC control register 1, bits 2:1 to have 512 BCLK cycles per frame. This would mean it is expecting a TDM 8 signal with 32 BCLK transitions per channel. If you are only sending 16 then it may be a problem. Also, is your data left justified or right justified?

    So also let me know the value of the other registers. You can also send a screenshot of the signals. Show the BCLK, LRCLK and data. I would like to see about 1 frame and a half on the screen for one shot. Then zoom in on the edge of the LRCLK and show it will about 8 or 10 BCLK cycles for another screenshot.

    Send a schematic of the DAC and the circuits around it.


    Dave T

  • Hi Dave,

    Thanks for your suggestion.

    Actually my configuration for AD1934 was correct. The issue was with my audio samples itself and wrong DMA configuration in my MCU.

    I re-sampled a 44.1kHz audio file into a 48kHz audio file using some software and somehow it broke the audio. I used an original 48kHz audio file and fixed my MCU's DMA settings and I could hear the audio without any issues.



  • Hello,

    I'm using the same codec but can't lock de PLL. Can you send a schematic with the pins connection please? Thank you.

  • Hello memo,

    Can you show us your schematic? For the PLL to lock you need to have a valid master clock or the registers set to route the LRCLK to the PLL input. Then you need the correct PLL filter. Then all the correct power and ground. I have seen poor PCB layouts cause issues with the PLL not locking. So the details are with what you are doing and how your PCB was implemented. The only way to help you is to have more information on your specific system details. 

    Dave T