AD7945 Digital Glitch from WR_n line

Question

I have an FPGA controlling a set of DAC chips, the AD7945, in a system updating at 1 MHz for time-varying ramps in the analog output. To mitigate digital impulse glitching, I have attempted to design the code to strobe the WR_n line out of phone with the main system clock, so that data is only latched when valid. However, by strobing WR_n, I see far more severe digital glitching on the output. Is there a subtlety to clocking the WR_n line that I am missing? The latency appears in the spec sheet to be well within the relevant timing that I'm attempting.

camacazio · Accepted Answer

The code to control this is generated by a Cyclone 4 FPGA, and the DAC is updated at 2 MHz (same results at 1 MHz rate). The routine is to update the DAC values for a specified time with update rate at the clock frequency, then pause. While the FPGA is calculating and updating outputs, the wr_n line is held low, and when idle, wr_n is high. Shown below has visible digital glitching when the wr_n is set to make the DAC transparent while updating. When I attempt to implement a timing such that wr_n only goes low when data is valid, the next picture with awful oscillations shows the results. In this case, I clock wr_n at the same rate as the DAC but with a 90 degree offset, such that it is high when DAC values update and low, transparent, after data is ready.)