I have an FPGA controlling a set of DAC chips, the AD7945, in a system updating at 1 MHz for time-varying ramps in the analog output. To mitigate digital impulse glitching, I have attempted to design the code to strobe the WR_n line out of phone with the main system clock, so that data is only latched when valid. However, by strobing WR_n, I see far more severe digital glitching on the output. Is there a subtlety to clocking the WR_n line that I am missing? The latency appears in the spec sheet to be well within the relevant timing that I'm attempting.
Another solution approach; does anybody have or want to collaborate towards FPGA design to better strobe the WR_n line?