Hello, help needed
Power-up sequence: Can VLOGIC and digital inputs power-up before VDD?
Hardware protection of EEPROM and RDAC register: How is this made? (not described in data sheet)
Timing on RESET pin: Data sheet say maximum 10us. Is this correct? What happen if pin is held low for several seconds? (I have no need to send or receive data during this time)
Apologies for the delayed response.
The data sheet strongly recommends the ideal power-up sequence which is GND, VSS, VDD, VLOGIC, digital inputs, and VA, VB, and VW. The order of powering VA, VB, VW, and digital inputs is not important as long as they are powered after VSS, VDD, and VLOGIC.
The hardware protection is a typo error. This will be removed on the next data sheet revision. Thank you for spotting this.
The RESET pin needs to be held a minimum of 10us to guarantee that the part detects the RESET pulse. If the part is held low for longer amount of time the part will remain in reset mode where in any SPI commands will be ignored until RESET is brought high again.