AD5726 reference voltages and power-up sequence

Hello support team,

1. The AD5726 datasheet says that the minimal negative reference voltage is -10V. On the other hand, typical application discussed throughout the datasheet utilizes +/-10V references. So it looks like the datasheet suggests working just at the lower limit of Vrefn, without any headroom. Can you comment on this?

2. In the power sequence section, it is recommended to apply the reference voltages after the AVss and AVdd. But in this case there will be a period of time with both Vrefp and Vrefn equal to zero, while the datasheet says Vrefp must exceed Vrefn by at least 2.5V. Is the power-up sequence an exception from this rule? Is it safe for the chip to have AVss=-15V, AVdd=+15V, and Vrefp = Vrefn = 0?

3. I'm considering a power-up sequence whereby the GND is always connected, then AVss and AVdd both rises linearly (but AVss at a faster rate) for 10 - 20 ms, and then both Vrefp and Vrefn are applied simultaneously. Is there anything wrong with this sequence?

4. I'm going to use AD688 as the reference source. Can I use pin #7 of this IC (used also for noise reduction) to turn the outputs on and off? I mean, if I connect this pin to GND via a FET, both outputs should go to zero, and return to +/-10V when the connection is removed. Is this OK?

Thanks in advance,

Michael 

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  • 0
    •  Analog Employees 
    on Oct 27, 2016 1:37 AM

    Hi Michael,

       


    1. The AD5726 datasheet says that the minimal negative reference voltage is -10V. On the other hand, typical application discussed throughout the datasheet utilizes +/-10V references. So it looks like the datasheet suggests working just at the lower limit of Vrefn, without any headroom. Can you comment on this?
    the VrefN voltage range is from -10V to VrefP-2.5V as specified in the table 2 of the datasheet where the  supplies are AVDD = 15V and AVSS = -15V. When setting the reference values please make sure that it is within the supplies. Figure 24 shows details, 0V min between VREFN and AVss can say that, AVss can go close to or equal to VrefN but VRefN cannot go to AVss, the minimum it can have is -10V
     

    2. In the power sequence section, it is recommended to apply the reference voltages after the AVss and AVdd. But in this case there will be a period of time with both Vrefp and Vrefn equal to zero, while the datasheet says Vrefp must exceed Vrefn by at least 2.5V. Is the power-up sequence an exception from this rule? Is it safe for the chip to have AVss=-15V, AVdd=+15V, and Vrefp = Vrefn = 0?

    Please follow the recommended power up sequence. The 2.5V apart for VrefN and VrefP would matter much on the accuracy and range of the AD5726 as shown in the figure 24 of the datasheet. The vrefn and vrefp sets the range

    3. I'm considering a power-up sequence whereby the GND is always connected, then AVss and AVdd both rises linearly (but AVss at a faster rate) for 10 - 20 ms, and then both Vrefp and Vrefn are applied simultaneously. Is there anything wrong with this sequence?

     I think this would work. Please take note on the max and min value of the AVss and AVdd , Vrefn and VrefP including 2.5V minimum difference

    4. I'm going to use AD688 as the reference source. Can I use pin #7 of this IC (used also for noise reduction) to turn the outputs on and off? I mean, if I connect this pin to GND via a FET, both outputs should go to zero, and return to +/-10V when the connection is removed. Is this OK?

      AD688 pin 7 is a noise reduction pin. A capacitor to ground must be connected to this to reduce noise or this pin can be left open. Cannot guarantee the performance of AD688 when this pin is connected to ground.

    Regards,

    Jonathan

Reply
  • 0
    •  Analog Employees 
    on Oct 27, 2016 1:37 AM

    Hi Michael,

       


    1. The AD5726 datasheet says that the minimal negative reference voltage is -10V. On the other hand, typical application discussed throughout the datasheet utilizes +/-10V references. So it looks like the datasheet suggests working just at the lower limit of Vrefn, without any headroom. Can you comment on this?
    the VrefN voltage range is from -10V to VrefP-2.5V as specified in the table 2 of the datasheet where the  supplies are AVDD = 15V and AVSS = -15V. When setting the reference values please make sure that it is within the supplies. Figure 24 shows details, 0V min between VREFN and AVss can say that, AVss can go close to or equal to VrefN but VRefN cannot go to AVss, the minimum it can have is -10V
     

    2. In the power sequence section, it is recommended to apply the reference voltages after the AVss and AVdd. But in this case there will be a period of time with both Vrefp and Vrefn equal to zero, while the datasheet says Vrefp must exceed Vrefn by at least 2.5V. Is the power-up sequence an exception from this rule? Is it safe for the chip to have AVss=-15V, AVdd=+15V, and Vrefp = Vrefn = 0?

    Please follow the recommended power up sequence. The 2.5V apart for VrefN and VrefP would matter much on the accuracy and range of the AD5726 as shown in the figure 24 of the datasheet. The vrefn and vrefp sets the range

    3. I'm considering a power-up sequence whereby the GND is always connected, then AVss and AVdd both rises linearly (but AVss at a faster rate) for 10 - 20 ms, and then both Vrefp and Vrefn are applied simultaneously. Is there anything wrong with this sequence?

     I think this would work. Please take note on the max and min value of the AVss and AVdd , Vrefn and VrefP including 2.5V minimum difference

    4. I'm going to use AD688 as the reference source. Can I use pin #7 of this IC (used also for noise reduction) to turn the outputs on and off? I mean, if I connect this pin to GND via a FET, both outputs should go to zero, and return to +/-10V when the connection is removed. Is this OK?

      AD688 pin 7 is a noise reduction pin. A capacitor to ground must be connected to this to reduce noise or this pin can be left open. Cannot guarantee the performance of AD688 when this pin is connected to ground.

    Regards,

    Jonathan

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