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AD5160 SPI parameters?

Hi,

What would be the correct settings to send data to the AD5160 via SPI. The datasheet tells me that the clock polarity is active low (CPOL = 1) and leading edge triggered (CPHA = 0) regarding the phase. Is this correct?

Thanks in advance!

Kind regards, Samuel Lourenço

  • Hi Samuel,

    CPOL=0 since the idle state is logic 0 for SCLK. Meanwhile CPHA=0 because data is valid on the rising edge of SCLK.

    Best regards,

    Rainier

  • Hi,

    An extra question strongly related to this: I need to have this working in SPI mode 3, as I have other devices on the bus, which only works with an inactive high CLK.
    When I look at the datasheet for AD5200, which is somewhat worded similarly in regards to the the interface section, it has a truth table, from which I can see that it would also work fine in SPI mode 3. Unfortnuately, AD5160 lacks this table.

     

    Can you please confirm whether or not the AD5160 will work just a reliably in SPI mode 3 (CPOL=1, CPHA=1) ?

    Thanks

  • Hi,

    You can refer the following table:

    CLK CSb Register Activity
    L L No Sr effect
    P L Shifts one bit in from SDI pin
    X P Loads SR data into RDAC latch
    X H No operation

    Since you CPOL=1, i think it will work with CPHA=1.

    Regards,

    Koushik