Layout of AD5687BCPZ

Hi Ben,

The analog and digital ground connections is always a controversial question so, let me explain/argument my opinion,

Internal digital and analog grounds are some times bond separately to improve energy dissipation... as you can imagine, at this levels of miniaturization the parasitic are not negligible so, physically, cannot achieve a zero ohms connection, and any internal energy transition will affect the  other block (analog - digital). In conclusion, to minimize this disturbance, ie digital crosstalk, separate bonding is used.

From a practical point of view, both grounds must be connected as close as possible to minimize current loops... in other words, analog can digital must be connected together at the output of the device... at this point, due to higher geometries used at the output, the impedance are smaller, so, disturbance can be minimized pretty good.

In your case, connect both GNDs to AGND.

Regards,

Miguel

Hi Miguel,

Thank you for the reply. It is very insightful.

This chip has 3 bias lines, namely Vref, Vlogic and VDD. I will bias the Vref from a precision voltage reference. Would it be possible to bias the Vlogic and VDD from the same supply? My concern is that the chip is on the analog ground and if I bias Vlogic from a digital supply, the return currents may be large compared to biasing both Vlogic and VDD from an analog supply. 

Thank you.

Regards,

Ben

Hi Ben,

Sorry about the delay.. I didn't get any email alert about your answer.

Yes, you can do BUT remember to add independent decoupling caps on each supply pin.

regards

Miguel