Post Go back to editing

[AD5322] Deasserting SYNCb before 16th clock edge


What should be happen in input shift register when SYNCb is deasserted before 16th falling edge of SCLK?

My expectation is that the content of the input shift register should be cleared and the content of the input register should not be changed. Is that right?

Best Regards,

Taiki Mineno