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Problem with AD5263

Hello,

For an application, I use 2 AD5263 in SPI (see attach, "Capture.PNG).

The frequency of the SPI input signal (SDIMESURES) is 2,5Mhz (see attach SDIMESURES2,5MHz).

The problem I have is that my signal is damaged on the output of the first AD5263 (SDOMESESURES2,5MHz, see attach) and even more on the output of the second AD5263 (POT2,5MHz, see attach).

How can I do to have steep fronts? I saw in the datasheet :

" It is recommended to increase the clock period when using a pull-up resistor to the SDI pin of the following device because capacitive loading at the daisy-chain node (SDO to SDI) between devices may induce time delay to subsequent devices"

I try to change my frequency to 1,25MHz, but nothing change, my fronts are also longer (SDOMESURES1,25MHz, see attach).

If you have any suggestions, I would be very happy :-). Excuse my poor English, I'm French.

Regards, Florian

attachments.zip
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  • Hi Florian,

    The pull-up resistor along with the input capacitance induces quite a lot of RC delay in the daisy chain. 

    Suppose the capacitance in the line is around 50pf( considering the wire, routing and input capacitance) and the the pull up resistance is 2.2K ohm, the RC time constant is around 110ns. It takes around 3 time constant to reach 90% of the voltage level, i.e. 330ns. The time period for 2.5Mhz SCLK is, 400ns. So, the RC delay is considerable for the SCLK frequency.

     

    There are two ways of solving it:

    1. Decrease the Value of the Pull-up resister. The trade off is that power dissipation through the pull-up resistor will be more.

    2. Further decrease the SCLK frequency.

    I hope that solves your problem.

    Regards,

    Koushik

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  • Hi Florian,

    The pull-up resistor along with the input capacitance induces quite a lot of RC delay in the daisy chain. 

    Suppose the capacitance in the line is around 50pf( considering the wire, routing and input capacitance) and the the pull up resistance is 2.2K ohm, the RC time constant is around 110ns. It takes around 3 time constant to reach 90% of the voltage level, i.e. 330ns. The time period for 2.5Mhz SCLK is, 400ns. So, the RC delay is considerable for the SCLK frequency.

     

    There are two ways of solving it:

    1. Decrease the Value of the Pull-up resister. The trade off is that power dissipation through the pull-up resistor will be more.

    2. Further decrease the SCLK frequency.

    I hope that solves your problem.

    Regards,

    Koushik

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