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Problem with AD5263


For an application, I use 2 AD5263 in SPI (see attach, "Capture.PNG).

The frequency of the SPI input signal (SDIMESURES) is 2,5Mhz (see attach SDIMESURES2,5MHz).

The problem I have is that my signal is damaged on the output of the first AD5263 (SDOMESESURES2,5MHz, see attach) and even more on the output of the second AD5263 (POT2,5MHz, see attach).

How can I do to have steep fronts? I saw in the datasheet :

" It is recommended to increase the clock period when using a pull-up resistor to the SDI pin of the following device because capacitive loading at the daisy-chain node (SDO to SDI) between devices may induce time delay to subsequent devices"

I try to change my frequency to 1,25MHz, but nothing change, my fronts are also longer (SDOMESURES1,25MHz, see attach).

If you have any suggestions, I would be very happy :-). Excuse my poor English, I'm French.

Regards, Florian
  • Hi Florian,

    I need two inputs from you, to help you out:

    1. What is the Vlogic Supply voltage?

    2. Can you give a screen shot of the CSb, SCLK and SDO signal pins of the first device. Please make sure that you stop the oscilloscope when you capture the waveform.



  • Hello koushik.kops,

    And thanks for your answer.

    1. What is the Vlogic Supply voltage? The supply of the device is +/-5V.

    2. Can you give a screen shot of the CSb, SCLK and SDO signal pins of the first device. Please make sure that you stop the oscilloscope when you capture the waveform. Please find in attach signals that you asked.



    Regards, Florian
  • Hi Florian,

    As per the datasheet you only need 20 bits in a frame to set the position of the wiper in the digipot for both device.

    I would like to know what data are you sending into the device.

    How many bits are you sending in a single frame?

    Can you share the waveform of CSb, SCLK, SDI and SDO in a single screen and send it? 



  • Hello koushik,

    I can't send you the waveform today, it will be tomorrow morning.

    A thing that I didn't say : there is a third device which is chained with the 2 AD5263 ; it's a DS1267S-10. I saw one thing ; the SPI signal which enters in it is very bad, but on the output, it is reformed.

    Concerning the frame, I will look at the program this afternoon, and I'll send you the information.

    Regards, Florian

  • Koushik,

    Please find the waveforms :

    • In yellow, SCLK.
    • In blue, CSb.
    • In pink, SDI.
    • In green, SDO.

    I did a Start/Stop on the oscilloscope, but I think there are a little of parasites.

    On my device, there are 2 boards with 3 devices which work in SPI (2 AD5263 and 1 DS1267S-10), so in all 6 devices (4 AD5263 and 2 DS1267S-10), and they are all chained.

    Regards, Florian

  • Hello koushik,

    I look at the program, and it's good. I send the good values, so I don't think that the problem comes from here.

    Regards, Florian

  • Hi Florian,

    The pull-up resistor along with the input capacitance induces quite a lot of RC delay in the daisy chain. 

    Suppose the capacitance in the line is around 50pf( considering the wire, routing and input capacitance) and the the pull up resistance is 2.2K ohm, the RC time constant is around 110ns. It takes around 3 time constant to reach 90% of the voltage level, i.e. 330ns. The time period for 2.5Mhz SCLK is, 400ns. So, the RC delay is considerable for the SCLK frequency.


    There are two ways of solving it:

    1. Decrease the Value of the Pull-up resister. The trade off is that power dissipation through the pull-up resistor will be more.

    2. Further decrease the SCLK frequency.

    I hope that solves your problem.



  • Hi koushik,

    Thanks for your answer, I will test this Thursday and I will say to you if it has worked.

    Regards, Florian

  • Hi koushik and sorry for the delay (holidays ^^)

    I test this afternoon with a new resistor value (R=330 Ohm), and it works, the fronts are very shorter.

    Thanks a lot ;-)