We have a board with 4 AD5570 DACs. They share the same control lines, except for SDIN. All four DACs are loaded and updated synchronously. The control is implemented in an FPGA.
On each update cycle, the output of the DACs produces a glitch of about 30-40 mV, on the time scale of 1-2 us. The DACs are updated once in every 10 us.
The glitch does not appear on the VREF input, or on the AGND with respect to DGND or the power supply lines. It seems to come from the DAC itself.
The glitches are very consistent in time and between devices. Their polarity, amplitude and timing doesn't change with the DC level of the output signal - they appear to be the same at +10 V, -10 V and 0V. They look similar to the datasheet description of a major code transition glitch; however, they appear anywhere within the range.
The digital interface was investigated, in particular the timing of the LDAC and SYNC signals. No issue was found there. In the attached figure, the signals show operation in synchronous LDAC update mode.
Some cross-talk from the digital lines to the output is evident during the data loading. However, it is much below the level of the observed glitches.
Does anyone have any idea what causes this glitches, and how we can get rid of them?
Cheers,
Nikolai
