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# DAC update rate

I plan to use AD5672, but the update rate is not described in parametric search and AD5672 data sheet.

DAC Parametric Search with update rate

http://www.analog.com/en/parametricsearch/10933#/p4910=Precision%20DAC&d=sel|0|4527|s8|4910|7|165|4458|3899|4737|4129|3970|s3|s5

How do I think the update rate?
(compare the slew rate and input shift register time (t1 x 24bit) and choose the longer time?)

Would you tell me the AD5672 update rate?

• Hi,

You can take a similar approach in computing the update rate in this thread:

Cheers,

Ivan

•

Q1.

It is described at AD5791 datasheet

T17 : /SYNC rising edge to output response time(/LDAC tied low) (datasheet Rev.D table 4)

Tsettle(Output Voltage Settling Time) : Output Voltage Settling Time is the amount of time it takes for the output voltage to settle to specified level for a specified change in voltage.(datasheet Rev.D P17)

It is described at AD5672R datasheet

T17 : (There is no equivalent parameter.)

Tsettle(Output Voltage Settling Time) : The output Voltage Settling Time is the amount of time it takes for the output of a DAC to settle to a specified level for a 1/4 to 3/4 full-scale input change and is measured from the rising edge of /SYNC.(datasheet Rev.B P22)

Q2.

What is the start point the settling time?

Would you tell me the difference between AD5672R/Figure 41 and AD5672R/Figure 51?

• Hi,

1) Please use the OUTPUT VOLTAGE SETTLING TIME spec in Table 4 as the Tsettle for AD5672R

2) Settling time starts from the /SYNC rising edge. As for the difference between Figure 41 and Figure 51, I'll get back to you on that.

Cheers,

Ivan

• Hi,

Figure 51 is a duplicate of Figure 41, we're going to remove Figure 51 on the next revision of the datasheet.

Cheers,

Ivan