In page 5 of AD5450/AD5451/AD5452/AD5453 data sheet, Timing Diagramis shown and looks like data is loaded into input shift register in MSB first manner.
in the serial interface example in page 21-22, looks like data is loaded in LSB first manner and when /SYNC go high after 12 valid clock edges, an incomplete data sequence of 12 bits(LSB) is loaded and to complete the shift register, the 4LSBs in the previous sequence is takenand used as the 4MSBs missing.
whould you teach me how data is loaed into input shift resister and the previous 4LSBs are used as 4MSBs step by step?
after control bits 11 are set, when is that effective in data loading? after /SYNC goes high and low(in the next data frame)?
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The data transmission should be MSB first. When control bits 11 are used, it will take effect on the next frame.