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Reading the AD5696R

I am investigating a problem we are having with reading from the AD5696R. When following the "read operation" procedure, the value returned is nearly always 0x91. I attached a Corelis BusPro-I I2C monitor to the EVAL-AD5696RSDZ and performed a read, and noticed that it did not seem to be following the procedure. When reading from DAC C, the command following the first address byte was 14, not 04 as I understood from the datasheet. Can you explain why I am seeing a different read operation than is described in the datasheet? 

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  • Hi ,

    Could you try this sequence if this will work for you please?

    When reading data back from the AD5696R DACs, the user begins with an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. This address byte must be followed by the COMMAND BYTE, which consists of the higher nibble COMMAND CODE = 0x9 or the READ INPUT REGISTER COMMAND, and the lower nibble DAC ADDRESS CODE equivalent to the DAC channel (multiple DAC channels not applicable), which is also acknowledged by the DAC. The COMMAND byte must then be followed by a 2 BYTE DUMMY DATA (0x0000 or 0xFFFF) to complete the write operation. Following this, there is a repeated start condition by the master and the address is resent with R/W = 1. This is acknowledged by the DAC, indicating that it is prepared to transmit data. Two bytes of data are then read from the DAC. A NACK condition from the master, followed by a STOP condition, completes the read sequence.

    Cheers,

    Ivan

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  • Hi ,

    Could you try this sequence if this will work for you please?

    When reading data back from the AD5696R DACs, the user begins with an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. This address byte must be followed by the COMMAND BYTE, which consists of the higher nibble COMMAND CODE = 0x9 or the READ INPUT REGISTER COMMAND, and the lower nibble DAC ADDRESS CODE equivalent to the DAC channel (multiple DAC channels not applicable), which is also acknowledged by the DAC. The COMMAND byte must then be followed by a 2 BYTE DUMMY DATA (0x0000 or 0xFFFF) to complete the write operation. Following this, there is a repeated start condition by the master and the address is resent with R/W = 1. This is acknowledged by the DAC, indicating that it is prepared to transmit data. Two bytes of data are then read from the DAC. A NACK condition from the master, followed by a STOP condition, completes the read sequence.

    Cheers,

    Ivan

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