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how to interface FPGA based FIFO MEMORY to AD5542A d/a ic ?

AD5542A d/a ic accepts input data via SPI. first one 16bit long sample is shifted in input shift register on rising edge of clock and t latch it to dac latch register we need  a low to high CS(active low) i. e we will need to provide some delay between each 16bit sample as to latch it and update dac by a low to high CS of duration 15 ns. we are storing data to be converted in a FIFO memory which give data serially without any gap between two 16bits samples. below is the timing diagram of AD5542A.