USE AD5725 3 line

Hi,

You could try this instead:

R/W: tie low

CLR: tie high

/LDAC: tie low

control /CS, A0, A1 through GPIOs.

When /LDAC is permanently tied low, the output will almost be immediately updated when /CS is low for a minimum time given by twcs.

Cheers,

Ivan

thank you for your answer.
Please tell me a little more.

When should I write data?
Writing with CS=L, then updating with CS=L⇒H⇒L?
(When CS=H, it was written as HOLD, so I think that it cannot be written at this time.)

Sorry I am not sure what exactly your question is, but data transition should follow thte Twds and Twdh timings as shown in the figure below. Same as for the A0/A1 transitions as well.

Basically, transition your data before pulling /CS = low (using Twds timing), and after releasing /CS=high using Twdh timing. Did I answer your question?

Cheers,

Ivan

thank you for your answer.

Let me check if my　understand the following

Is tas the recognition that the address must be fixed before CS = Low?
(The address is read when CS=Low)

Since the data is also included when CS=low, do I understand that the input data must be confirmed before twds time before CS=Low?

And since data is taken in over twcs (10ns), it is necessary to keep CS low for that time or longer.

Is it a recognition that I should not change the data during tAH and tWDH time just in case after CS=H?

UBOTI said:

Is tas the recognition that the address must be fixed before CS = Low?
(The address is read when CS=Low)

Yes, the address must not change within tas

UBOTI said:

Since the data is also included when CS=low, do I understand that the input data must be confirmed before twds time before CS=Low?

Yes this is correct.

UBOTI said:

And since data is taken in over twcs (10ns), it is necessary to keep CS low for that time or longer.

Is it a recognition that I should not change the data during tAH and tWDH time just in case after CS=H?

There should be no data transition or change during twdh

Thank you for your answer

Thank you for your answer