AD7847

Hi maggie

The third timing could work but the T4 and T5 timings are going to be referenced with respect to /CS rising edge.

You can just tie /WR and /CS so they will change state at the same time to simplify your implementation.

Cheers,

Ivan

Hi, Ivan,

Thanks for your reply.

Is the "The third timing" you mentioned is the one below?

So the timings could not work if the CS is activated later than WR?

Such as the one below.

Currently I could not tie CS and WR together due to some hardware design reasons.

So I am looking into this timing problem to get the best solution for the timings.

Looking forward to your reply.

Thanks!

Maggie

Hi maggie,

Yes that is the third timing I was referring to.

As for /CS pulled low later than /WR, this may still work if Figure 11 is to be followed, however, it might take time to confirm this as the part is very old. Are you open to consider other parts?

Cheers,

Ivan

Hi,Ivan,

Thanks for your replay.

Currently I can not replace the part since we are working on an old project...

And, "figure 11" in your reply seems a little confusing since I don't know which one it is.

BR,

Maggie

Hi maggie,

Sorry I was referring to Figure 11 of data sheet.

If this is to be followed, it does not matter whichever signal goes logic low first. However, this is a simplified block diagram so there are other things which we might not know about. Which is why we lean on the safer side where /CS goes low first before /WR, or both /CS and /WR go low at the same instance.

Cheers,

Ivan

Hi, Ivan,

Thanks!

I agree with you that from figure 11 above, wr and cs can be altered. however, from you suggestion, I will follow the safer side.

Br,

Maggie