AD5370 Performance

I have been playing around with AD5370 through various methods, and I simply cannot get a high-performance throughput from it. What I mean is the time taken to update a voltage on the DAC output pin. Through various experiments via various approaches, I find that the eval board's chip can only update about at a rate of one per millisecond. I have used three methods.

  1. EVAL boards onboard cypress USB chip with CYUSB (AD) provided driver (1.13 ms)
  2. EVAL boards onboard cypress USB chip with LIBUSB drivers (open source)(0.95 ms)
  3. Direct SPI communication using Raspberry Pi 3 - with 50 Mhz SPI clock    (~1ms)

From what I understand from the chip description, the chip supports SPI up to 50Mhz, or 50 million bits per second, each word that is sent across is 24 bits long (8bit address + 16-bit data),  

SPI max speed = 50 Mhz
SPI max bit rate = 50 million bps
SPI word length = 24 bits
SPI max words per second = 50 million / 24 or 2.083 million words per second
Number of channels on board = 40
Let us assume a parallel update to all 40 channels at a time, or the registers are blocked with others are written to.

=> 2.083 M / 40 per channel, or 52.083 Khz, which means the best timing I should get is 1/52083 or 0.0000192 seconds, or 0.019 ms or 19 microseconds or 19200 nanoseconds 

As per the datasheet, the performance of register updates rates is, in three stages, first two takes 600 ns, the third stage takes 300 ns, almost a total of 900ns, let's give it a 4x time benefit. And round generously, we get one update every ~4000 ns, which is far lower than the SPI speed capacity. 

So as per the register update rates, we should get ~5000ns per new sample (with generous allowances) and ~20000 nanoseconds per SPI speed limits, which is about 0.02 milliseconds. My results are off by a factor of 50. Either there is something seriously wrong in my math or my approach. 

  • Can you help me figure out what's wrong in my math, or my method? 
  • I have tested by using an oscilloscope that can support up to 60 MHz, (Tektronix TBS1064)  with a raspberry pi 3 (with reduced SPI speed of 50 Mhz)
    • You can see the SCLK is working at about 20-25 ns (LEFT image)
    • You can see the Vo Output is at-best at one millisecond (RIGHT IMAGE)
      • Output pulse width is about 2x 500 microsecond or ~1ms
      • I am cycling two voltage values here. 
  • What are my options here...

Any help guidance and thoughts would be deeply appreciated. 

  • 0
    •  Analog Employees 
    on Apr 29, 2020 9:44 AM 10 months ago


    Would you mind sharing with me the commands you were writing over the SDI line that resulted with the output above?

    Kind regards,


  • Hello Erick, 

    What I have been trying to do is use this code, in the main function I loop through ac.write_value_volt(1,x%2); which results in the spi transfer of 

    [201, 85, 84] or [C95554]
    [201, 98, 32] or [C96220]
    [201, 85, 84] or [C95554]

    (Note LK4 is position B)

    In my previous image, the top part of the wave takes ~1ms, which I believe could the way python is looping through or something funny about my code. 

    I do see my pulse width of ~62.5 microseconds. Which is about 16 kHz.Which is way faster than ~1ms, but I would like to know the theoretical and practical limitations of the system. 

  • 0
    •  Analog Employees 
    on Apr 30, 2020 5:50 AM 10 months ago in reply to sandeepzgk


    Basically, since you are writing a series of commands continually, one thing that should be considered in this case is the state of the /BUSY pin. 

    The /BUSY pin goes low for a certain period of time after each time the user writes new data to the corresponding X1, C, or M register and the output updates only when it goes back to HIGH again. 

    Can you monitor the /BUSY and SDI pins to make sure that the /BUSY low time has finished before the succeeding command (24bits)?

    Kind regards, 

  • I, unfortunately, have only one probe so I cant probe two things at the same time. But can you help me with the practical update frequency of the device... Because I want to know that solidly before proceeding. I have been working on this board for about ~3-4 months and I still haven't got a solid answer for this. 

    With a good SPI master, what is the update frequency I can get with this device? Per-channel, and all channel.

  • +1
    •  Analog Employees 
    on May 4, 2020 9:21 AM 9 months ago in reply to sandeepzgk

    As per the datasheet's timing, the maximum update rate of the device would be
    Update Rate = 1/(t5 + t4 + 23*t1 + t6 + t9 + t10 + t14 + t17)
    = 1/{20ns + 11ns + 23*20ns + 10ns + 42ns + [((N+ 1) × 600 ns) + 300 ns] + 3000ns + 20000ns}
    Where N = number of channels to be updated.
    Note that this timing includes t17 which is the DAC Output settling time to ensure that the output has already reached its desired voltage before writing another command. 

    However, you may start writing the next 24 command bits right after the /BUSY rising edge given that [t5 + t4 + 23*t1 + t6 + t9 + t10] is longer than [t14 + t17].

    Kind regards,