I have a few questions regarding the AD5292 or AD529:
While I assumed that the high voltage at the EXT_CAP pin is only needed to burn the fuses of the NV memory, it still seems to be generated during fuse readback.
This had me wondering if the high voltage is not only needed for reedback of the fuses via the SPI interface, but also during power-up or a dedicated reset.
If that would be the case, then I would need to be able to supply the 25mA pulse on VLogik not only during programming (e.g. being able to supply it externally when the circuit is to be calibrated), but also in the normal working circuit, at least at power-up.
What supported this wondering, was the fact that the AD5293 also needs the external 1µF capacitor at EXT_CAP, even though it is not programmable with non-volatile settings.
If this is the case, will the internal charge pump that generates this high voltage be running in the background all the time (possibly generating EMI), or will it only run for a short time during power-up and reset and will be completely shut off during the rest of the IC's operational time?
Except for programming the NV memory (and maybe during power-up and reset as wondered above), the current requirement of VLogic is quite low.
I wondered if it would be possible to dispense with a dedicated 3.3V or 5V regulator and just supply the VLogic pin from the 15V VDD supply via a resistive vltage divider.
With 25mA pulse current for 550µs (Figure 49 in the datasheet shows that the current is even not 25mA for all of the 550µs, but rather an average 15mA) and 2.5µF of capacitance, the VLogic would drop only 550mV, which might be perfectably acceptable with an idle VLogic of 5V, as VLogic only has to be above 2.7V.
With 5 devices connected in parallel, each of them having a 1µF capacitor across it's VLogic and programmed at a different time, this should work.
On the other hand, if the high voltage is also needed at power-up, the 5 switches would draw the necessary current simultaneously and therefore there would have to be more capacitors.
The possible problems I see here:
At power-up, the readout sequence is presumably initiated once a certain voltage at VLogic is exceeded (maybe some 2.5V in order to be fully functional from 2.7 to 5.5V).
If VLogic now drops by a certain amount, due to the current required for the generation of the high voltage at the EXT_CAP pin, and this drop exceeds a presumably built in hysteresis, some kind of oscillation might be startet, resulting in improper power-up of the circuit.
So in order to be able to supply enough capacitance, this biult-in hysteresis would have to be known.
Can you confirm the hypothesized behavior and maybe provide me with the according hysteresis voltage?
I also thought about connecting an 11V z-diode between VDD and VLogic in order to generate some 4V, but I wondered if the 4V would carry too much zener-noise.
Is there any possibility that noise from the VLogic could couple into the signal terminals? Does the exact voltage at VLogic have any influence on the function of the device (other than maybe some clock speed issues during SPI communication)?
Would it be ok, to supply VLogic with 5V via a resistive voltage divider from a 15V VDD and just connect an 11V z-diode in parallel with the upper resistor? That way I could have a clean 5V VLogic for normal circuit operation, while clamping VLogic to at least 3.5V during fuse blowing at power-up or reset.
1. During the entire operation of AD5292, the EXT_CAP pin must have 1uF capacitor with high voltage rating >= 7V. This is mentioned in Table 10 in the DS and in the EXT_CAP CAPACITOR section. Same is true for AD5293. There is no internal charge pump circuit here. Other than the digital interface running on Vlogic, all other blocks including memory blocks are running on Vdd/Vss. Refer to Figure 49 for the OTP current requirement. High Vdd current requirement is for a short duration during OTP read/write for AD5292 and during power-up/reset. During the normal operation, OTP is not accessed at all and so current through Vdd will be as given in the DS.
2. The most part of the second question is not valid, based on the above statement. Typical 25mA OTP current spec is on VDD and not on Vlogic. Please refer to Figure 49. It is Idd current and not Ilogic current.
Thank you SOO MUCH for clarifying this!
I think I was mislead by the Specification tables on page 3 and page 6, where with "OTP Store Current" and "OTP Read Current" it reads "ILOGIC_PROG" and "ILOGIC_FUSE_READ" in column 2, stating 25mA in column 4, after having stated 1 to 10µA for "ILOGIC" in the line directly above for the Logic Supply Current.
Although I notified the "Idd" in Figure 49, I kind of trusted the specification table more, as errors are more common in the figure description than in the specification table.
Maybe you should change the datasheet and rename "ILOGIC_PROG" and "ILOGIC_FUSE_READ" to "IDD_PROG" and "IDD_FUSE_READ".
There is something else in the datasheet that may be erroneous:
Note 7 and note 8 after the specification table state the same time for the duration of the increased supply current (both times 550µs), while Figures 54 and 55 show different durations for the voltage at EXT_CAP to be raised. But maybe the increased supply current is just needed in order to load the external 1µF capacitor and the duration for loading it is not dependent on how long the voltage is being held at that potential.But then again, there would be no need to make two different footnotes...
Regarding VLogic: I assume that I can indeed supply this pin with about 5V with a resistive voltage divider from the VDD pin (plus an appropriate decoupling capacitor). Is this correct?
I just wonder why you not just apply an internally regulated voltage to that pin. That could have been 2.6V supplied through an emitter follower, so one could supply it with an external 2.7 to 5.5V if one would want to.
Another suggestion for similar devices in the future:
The _RESET pin should be connected to VLogic if not used. It might be neat to not put such a pin on the very opposite side of the package with regard to the pin it shall be connected to if not needed.
Or just put a weak pull-up current to such a pin...
I assume there is no such (undocumented) weak pull-up of the _RESET pin in the AD5292? Or is there?
What happens if I tie the _RESET pin to GND instead? Does the device never start to function? (e.g. is the reset state- or edge triggered?)
Thanks for your suggestion.
Yes, you can use a resistive voltage divider to generate 5V. However do note that there will be noise on the Raw side during the digital transaction. Additionally power-up sequence needs to be followed as given in the datasheet. Additionally, the device may need software reset post power-up to ensure the correct configuration.
There is no internal pull up on the RESET pin.
If RESET is LOW, the device will always be in default state and any digital transaction will not have any impact on the device blocks.
I assume it is better if VLogic powers up a little later than VDD, because, according to the datasheet, after VLogic is powered, the power-on reset activates and restores the 20 TP memory.
For this the device actually needs VDD, so I assume VLogic has to come up either together with VDD or a bit after VDD, right?
As I would need to decouple the resistive voltage divider at VLogic anyway, VLogic would come up after VDD, so everything should be fine. At least as long as any digital high signals do not appear before VLogic has risen above 2.7V, right?
Reset is a digital input, so it is not ok for it to go higher than VLogig, right? So it's not possible to pull it to VDD? How about a quite high resistor. I assume there is a diode between _RESET and VDD. If I restrict the current to about 10µA (a 1 MegOhm resistor to VDD), would that be OK? Wiring a trace to the other side of the chip would really disturb signal flow and I would like to keep the planes on the other layers as intact as possible. VDD, on the other hand, is present on this side of the device anyway.
Yes, Vlogic has to come up either together with VDD or a bit after VDD.
All digital input VIH should be below or equal to VDD during the entire operation of the device.
You can tie RESET to Vlogic through a resistor in between.