AD5292 VLogic requirements and behavior during normal operation


I have  a few questions regarding the AD5292 or AD529:

While I assumed that the high voltage at the EXT_CAP pin is only needed to burn the fuses of the NV memory, it still seems to be generated during fuse readback.

This had me wondering if the high voltage is not only needed for reedback of the fuses via the SPI interface, but also during power-up or a dedicated reset.

If that would be the case, then I would need to be able to supply the 25mA pulse on VLogik not only during programming (e.g. being able to supply it externally when the circuit is to be calibrated), but also in the normal working circuit, at least at power-up.

What supported this wondering, was the fact that the AD5293 also needs the external 1µF capacitor at EXT_CAP, even though it is not programmable with non-volatile settings.

If this is the case, will the internal charge pump that generates this high voltage be running in the background all the time (possibly generating EMI), or will it only run for a short time during power-up and reset and will be completely shut off during the rest of the IC's operational time?

Second question:

Except for programming the NV memory (and maybe during power-up and reset as wondered above), the current requirement of VLogic is quite low.

I wondered if it would be possible to dispense with a dedicated 3.3V or 5V regulator and just supply the VLogic pin from the 15V VDD supply via a resistive vltage divider.

With 25mA pulse current for 550µs (Figure 49 in the datasheet shows that the current is even not 25mA for all of the 550µs, but rather an average 15mA) and 2.5µF of capacitance, the VLogic would drop only 550mV, which might be perfectably acceptable with an idle VLogic of 5V, as VLogic only has to be above 2.7V.

With 5 devices connected in parallel, each of them having a 1µF capacitor across it's VLogic and programmed at a different time, this should work.

On the other hand, if the high voltage is also needed at power-up, the 5 switches would draw the necessary current simultaneously and therefore there would have to be more capacitors.

The possible problems I see here:

At power-up, the readout sequence is presumably initiated once a certain voltage at VLogic is exceeded (maybe some 2.5V in order to be fully functional from 2.7 to 5.5V).

If VLogic now drops by a certain amount, due to the current required for the generation of the high voltage at the EXT_CAP pin, and this drop exceeds a presumably built in hysteresis, some kind of oscillation might be startet, resulting in improper power-up of the circuit.

So in order to be able to supply enough capacitance, this biult-in hysteresis would have to be known.

Can you confirm the hypothesized behavior and maybe provide me with the according hysteresis voltage?

I also thought about connecting an 11V z-diode between VDD and VLogic in order to generate some 4V, but I wondered if the 4V would carry too much zener-noise.

Is there any possibility that noise from the VLogic could couple into the signal terminals? Does the exact voltage at VLogic have any influence on the function of the device (other than maybe some clock speed issues during SPI communication)?

Would it be ok, to supply VLogic with 5V via a resistive voltage divider from a 15V VDD and just connect an 11V z-diode in parallel with the upper resistor? That way I could have a clean 5V VLogic for normal circuit operation, while clamping VLogic to at least 3.5V during fuse blowing at power-up or reset.

Best Regards,


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