Post Go back to editing

AD5676 SPI output

Hi,

I have a couple of questions concerning the above device.

1.  We would like to drive the SCLK continuously in our application.

Can you please confirm that the SYNC input internally gates the SCLK in the device?

This is implied by the description but it is not explicit.

2. We want to verify that we are communicating with the DAC as part of our BIT strategy.

I believe we can do this either by setting daisy chain mode, or performing a read back operation.

Both require 2 operational cycles to get the data out of the SDO port. Is there any difference in timing between the two modes?

For our application (interface is with a FPGA) it would be easier I think to verify the SPI link to the device using daisy chain mode as we would be getting back the same data that we are sending, albeit with an operational cycle delay.

Thanks Pete

Parents
  • Hi,

    1) Yes, the device will disregard clock cycles if /SYNC pin is high.

    2) Would like to clarify, what do you mean by BIT strategy?

    Daisy chain: whole 24-bit frame gets pushed out to the next frame through SDO regardless of command

    Readback: A readback command (0x9) is required in order to activate readback mode and a selected channel should also be defined. The next frame will contain the DAC register content of the channel, these are the contents of 16-bit LSB.

    Cheers,

    Ivan

  • Hi Ivan,

    Thanks for the clarification.

    BIT is Built in Test, which we perform after reset to check the peripherals to our FPGA are working.

    Cheers Pete

Reply Children
No Data