I have a couple of questions concerning the above device.
1. We would like to drive the SCLK continuously in our application.
Can you please confirm that the SYNC input internally gates the SCLK in the device?
This is implied by the description but it is not explicit.
2. We want to verify that we are communicating with the DAC as part of our BIT strategy.
I believe we can do this either by setting daisy chain mode, or performing a read back operation.
Both require 2 operational cycles to get the data out of the SDO port. Is there any difference in timing between the two modes?
For our application (interface is with a FPGA) it would be easier I think to verify the SPI link to the device using daisy chain mode as we would be getting back the same data that we are sending, albeit with an operational cycle delay.