AD5293 Update not occurring

Hello

Working with a board that uses 2 AD5293 digital potentiometers.

One part accepts an update of the resistance value, the other does not, even though I'm controlling both of them the same way.  The resistance value of that pot doesn't move from 10K

Below is a waveform displaying all of the signal pins of the pot that is NOT updating.  

What are possible causes for a pot wiper value not changing?

Thanks

Parents
  • 0
    •  Analog Employees 
    on Jan 16, 2020 5:50 AM

    Hi,

    Can you share the schematic of the circuit? It would help me debug better.

    Regards,

    Koushik

  • Sorry here is the relevant schematic.

    All of the I/O pins (pins 1, 10, 11, 12, 13, 14) are connected directly to Xilinx Spartan 6 FPGA I/O pins configured as follows:

    IOSTANDARD = LVCMOS33

    DRIVE = 12 (12 mA)

  • So the whole benefit of putting SCLK high when SYNC is high is just the saved quiescent current of the digital input stage, right?

    It would be nice if that was mentioned somewhere in the datasheet, because it might make designing the interface much easier if the 80µA are irrelevant for the design.

    I just wanted to add a major THANK YOU for your efforts and your patience with our sometimes crazy problems.

  • 0
    •  Analog Employees 
    on Jul 10, 2020 5:26 AM in reply to GerdF

    That is not correct. In a CMOS logic gates, quiescent current will not be that high whether the input is held low or high. 

    There is no mention of any  SDO pull-up value or the SDO state whether in tri-state or any logic levels in the figure. Else the 80uA current will violate the current limits in the spec table.

    For the datasheet, the numbers mentioned in the spec table are the valid ones, as all conditions are mentioned explicitly at the top or in the comment columns. For the Figures, the conditions are not stated clearly in many cases and it can cause mis-interpretations if not used in the right context.

  • So I wonder what Figure 23 wants to tell us.

    It somehow looks like the input current of a CMOS logic gate superimposed with an 80µA weak pull-up current source.

    Also Figure 23 is about digital inputs, so rather DIN, SCLK or SYNC than SDO.

    But speaking of SDO... Maybe the chip designer wanted to add a weak pull-up to SDO (quite neat idea) but somehow it ended up on one (or more than one) of the other digital input pins.
    As mask changes are really expensive and a weak pull-up at the SDO pin is not necessary, it might have been decided to just let the chip design at it is and note the current in figure 23.

    But then the digital input's input current at 0V, which is stated as +-1µA would be 80µA.
    So maybe figure 23 might be erroneous after all or it just describes a weird condition we do not know of.

  • 0
    •  Analog Employees 
    on Jul 10, 2020 2:28 PM in reply to GerdF

    Your theories are not correct.. There are no pull ups on the input pins because had it been there, it will be permanent and it can not go from 80uA to 1uA without having any configuration update, and such configuration register does not exist.

    If you have the device, you will be able to confirm what the actual current is. 

  • I just tried to find an explanation for the graph in figure 23.

    A pull-up would not have to be permanent if it is a current source with a pmos transistor, because with increasing input voltage the VDS of the transistor would decrease and the current would also decrease once the transistor goes from saturation into the linear region and eventually it would go to zero.
    I don't say there has to be a pull-up, but that would be an explanation of figure 23. It could also be due to some internal level shifter, because somehow the inputs referring to Vlogic and GND have to result in signals controlling FETs that are connected to VDD and VSS...

    Unfortunately, due to Covid-19 I don't have access to the lab, so I can't measure anything. That's why I have to rely so heavily on the datasheet and the information I am given here, and that's also why I am asking so many detailed and weird questions.

    I have to deliver the schematic and layout for the boards to be ordered and I also have to make a parts list for the first prototype boards. I hope I can at least measure the prototypes and don't have to approve building thousands of boards being built without measuring stuff beforehand.

    Now there is figure 23 and I need to know what it tells and how reliable the information in the datasheet is.

    I took a look at a few other AD parts in order to get a clue:

    AD5270: Figure 24: Looks similar to figure 23 of the AD5293, although the current a t 0v is even almost 400µA.

    AD5174: Figure 10: Looks almost the same as figure 24 of the AD5270.

    With both of the above this is not matching to the value given in the specification table.

    AD5290: Figure 23: Also shows a peak at 1.5V digital input voltage, but goes down to 15µA at both, 0-1 and 3-5V. The 15µA stated as being typical in the specification table, though.

    AD5123: Figure 16: The shape looks more like the one in figure 23 of the AD5293, although it is shifted a bit to higher voltages and the current returns to almost zero below 1v, which the curve in fig 23 of the AD5293 doesn't.

    AD5260: Figure 22: Peak is much wider and not that spiky and this one does not return to zero, neither with 0v nor with 5v digital input voltage. Ilogic is specified 60µA max, which is definitely higher than what is specified for the AD5293, but still the current drawn in figure 22 of the AD5260 is higher than the specified 60µA.

    So there are definitely some issues with those datasheets.
    I really don't care if there were some errors or mix-ups made with the numbers or scales or graphs. We all are humans and stuff happens. I just need to know how the device really behaves.

Reply
  • I just tried to find an explanation for the graph in figure 23.

    A pull-up would not have to be permanent if it is a current source with a pmos transistor, because with increasing input voltage the VDS of the transistor would decrease and the current would also decrease once the transistor goes from saturation into the linear region and eventually it would go to zero.
    I don't say there has to be a pull-up, but that would be an explanation of figure 23. It could also be due to some internal level shifter, because somehow the inputs referring to Vlogic and GND have to result in signals controlling FETs that are connected to VDD and VSS...

    Unfortunately, due to Covid-19 I don't have access to the lab, so I can't measure anything. That's why I have to rely so heavily on the datasheet and the information I am given here, and that's also why I am asking so many detailed and weird questions.

    I have to deliver the schematic and layout for the boards to be ordered and I also have to make a parts list for the first prototype boards. I hope I can at least measure the prototypes and don't have to approve building thousands of boards being built without measuring stuff beforehand.

    Now there is figure 23 and I need to know what it tells and how reliable the information in the datasheet is.

    I took a look at a few other AD parts in order to get a clue:

    AD5270: Figure 24: Looks similar to figure 23 of the AD5293, although the current a t 0v is even almost 400µA.

    AD5174: Figure 10: Looks almost the same as figure 24 of the AD5270.

    With both of the above this is not matching to the value given in the specification table.

    AD5290: Figure 23: Also shows a peak at 1.5V digital input voltage, but goes down to 15µA at both, 0-1 and 3-5V. The 15µA stated as being typical in the specification table, though.

    AD5123: Figure 16: The shape looks more like the one in figure 23 of the AD5293, although it is shifted a bit to higher voltages and the current returns to almost zero below 1v, which the curve in fig 23 of the AD5293 doesn't.

    AD5260: Figure 22: Peak is much wider and not that spiky and this one does not return to zero, neither with 0v nor with 5v digital input voltage. Ilogic is specified 60µA max, which is definitely higher than what is specified for the AD5293, but still the current drawn in figure 22 of the AD5260 is higher than the specified 60µA.

    So there are definitely some issues with those datasheets.
    I really don't care if there were some errors or mix-ups made with the numbers or scales or graphs. We all are humans and stuff happens. I just need to know how the device really behaves.

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