I have a application which need to combine 2 ADN2850 with single SPI bus to a master controller.
But the timing diagrams on specification document shows up SDO=high while CS/ = high
I have not get sample yet to check if SDO=high@CS/=high
Is it right or not that SDO keep high while not being selected?
Can I combine 2 ADN2850 on same SCK/MISO/MOSI bus with 2 different CS/ ?